蓄电池

A 5GHz Floating Point Multiply-Accumulator in 90nm Dual V{sub}T CMOS；A high effective algorithm of 32-bit multiply and MAC instructions' VLSI implementation with 32 × 8 multiplier-accumulator in DSP applications；A high effective algorithm of 32-bit multiply and MAC instructions' VLSI implementation with 32×8 multiplier-accumulator in DSP applications；A Study on Hydraulic Active Engine Mount；A study on the cycle performance of lithium secondary hatteries using lithium nickel-cobalt composite oxide and graphite/coke hybrid carbon;A STUDY ON THE DEGRADATION MECHANISM OF Li{sub{2.6Co{sub}0.4N AS AN ANODE FOR Li SECONDARY BATTERIES;

基于重构技术的并行乘法累加器结构

实时信号处理系统要求数字信号处理器具有更高的速度和更低的功耗。文章提出的新型乘法累加器,具有在不同模式下分别处理16位与32位数据,或16位与32位数据混合运算能力。本运算结构采用由三个16位乘法器重构一个32位运算单元,可调用其中一至三个乘法累加模块处理不同精度的数据达到了高速度、低功耗的设计要求。在32位工作模式下数据处理速度可以达到16位乘累加器的水平。