Ka-band broadband filtering packaging antenna based on through-glass vias (TGVs)

This work presents a novel design of Ka-band(33 GHz)filtering packaging antenna(FPA)that features broadband and great filtering response,and is based on glass packaging material and through-glass via(TGV)technologies.Compared to traditional packaging materials(printed circuit board,low temperature co-fired ceramic,Si,etc.),TGVs are more suitable for miniaturization(millimeter-wave three-dimensional(3D)packaging devices)and have superior microwave performance.Glass substrate can realize 3D high-density interconnection through bonding technology,while the coefficient of thermal expansion(CTE)matches that of silicon.Furthermore,the stacking of glass substrate enables high-density interconnections and is compatible with micro-electro-mechanical system technology.The proposed antenna radiation patch is composed of a patch antenna and a bandpass filter(BPF)whose reflection coefficients are almost complementary.The BPF unit has three pairs ofλg/4 slots(defect microstrip structure,DMS)and twoλg/2 U-shaped slots(defect ground structure,DGS).The proposed antenna achieves large bandwidth and high radiation efficiency,which may be related to the stacking of glass substrate and TGV feed.In addition,the introduction of four radiation nulls can effectively improve the suppression level in the stopband.To demonstrate the performance of the proposed design,a 33-GHz broadband filtering antenna is optimized,debugged,and measured.The antenna could achieve|S11|<-10 dB in 29.4‒36.4 GHz,and yield an impedance matching bandwidth up to 21.2%,with the stopband suppression level at higher than 16.5 dB.The measurement results of the proposed antenna are a realized gain of~6.5 dBi and radiation efficiency of~89%.

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

TSV Minimization for Circuit Partitioned 3D SoC Test Wrapper Design

Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and

Analysis and optimization of TSV–TSV coupling in three-dimensional integrated circuits

Through silicon via （TSV）-TSV coupling is detrimental to the performance of three-dimensional （3D） integrated circuits （ICs） with the major negative effect of introducing coupling noise. In order to obtain an accurate estimation of the coupling level from TSV-TSV in the early design stage, this paper first proposes an impedance- level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV-TSV coupling effect. The accuracy of the formula is validated by comparing the results with 3D full-wave simulations. Furthermore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV-TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical pertbrmance of3D ICs.

Design of a 3D Wilkinson power divider using through glass via technology

Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,through glass vias(TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed.Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.

Design,analysis and test of high-frequency interconnections in 2.5D package with silicon interposer

An interposer test vehicle with TSVs（through-silicon vias） and two redistribute layers（RDLs） on the top side for 2.5D integration was fabricated and high-frequency interconnections were designed in the form of coplanar waveguide（CPW） and micro strip line（MSL） structures. The signal transmission structures were modeled and simulated in a 3D EM tool to estimate the S-parameters. The measurements were carried out using the vector network analyzer（VNA）. The simulated results of the transmission lines on the surface of the interposer without TSVs showed good agreement with the simulated results, while the transmission structures with TSVs showed significant offset between simulation and test results. The parameters of the transmission structures were changed,and the results were also presented and discussed in this paper.

New de-embedding structures for extracting the electrical parameters of a through-silicon-via pair

Two innovative de-embedding methods are proposed for extracting an electrical model for a through- silicon-via （TSV） pair consisting of a ground-signal （GS） structure. In addition, based on microwave network theory, a new solution scheme is developed for dealing with multiple solutions of the transfer matrix during the process of de-embedding. A unique solution is determined based on the amplitude and the phase characteristic of S parameters. In the first de-embedding method, a typical ＂π＂ type model of the TSV pair is developed, which illustrates the need to allow for frequency dependence in the equivalent TSV pair Spice model. This de-embedding method is shown to be effective for extracting the electrical properties of the TSVs. The feasibility of a second de-embedding method is also investigated.

Propagation delay and power dissipation for different aspect ratio of single-walled carbon nanotube bundled TSV

Through-silicon vias （TSVs） have provided an attractive solution for three-dimensional （3D） integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output （I/O） den- sity and improved system performance. This paper investigates the propagation delay and average power dissipation of single-walled carbon nanotube bundled TSVs having different via radius and height. Depending on the physical configuration, a comprehensive and accurate analytical model of CNT bundled TSV is employed to represent the via （vertical interconnect access） line of a driver-TSV-load （DTL） system. The via radius and height are used to estimate the bundle aspect ratio （AR） and the cross-sectional area. For a fixed via height, the delay and the power dissipation are reduced up to 96.2% using a SWCNT bundled TSV with AR = 300 ： 1 in comparison to AR = 6：1.

High-speed through-silicon via filling method using Cu-cored solder balls

A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture.Cu-cored solder balls with a total diameter of 100μm were used to fill 150μm deep,110μm wide vias in silicon.The wafer-level filling process can be completed in a few seconds,which is much faster than using the traditional electroplating process.Thermo-mechanical analysis of via filling using solder,Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials.It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.

AN EFFECTIVE DETAILED ROUTING ALGORITHM CONSIDERING ADVANCED TECHNOLOGY NODES

Detailed routing has become much challenging in modern circuit designs due to the extreme scaling of chip size and the complicated design rules.In this paper,we give an effective algorithm for detailed routing considering advanced technology nodes.First,we present a valid pin-access candidates generation technology for handling complex pin shapes.Then,we propose a tree-based nets components selection algorithm to decide connecting order for multiple nets components.Finally,combined with global routing results and advanced technology nodes,an initial routing results optimization algorithm is presented to achieve the final detailed routing results.Experimental results on industry benchmarks show that,our proposed algorithm not only achieves 100%routability on real industrial cases in a reasonable runtime,but also optimizes total wirelength,total vias and other advanced technology nodes simultaneously.