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Functional Verification Based on FPGA for AVS Video Decoder 被引量:1
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作者 FU Fang-fang YI Oing-ming SHI Min 《Semiconductor Photonics and Technology》 CAS 2009年第4期219-224,共6页
In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles... In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle. 展开更多
关键词 FPGA verification AVS video decoder MATLAB
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Design and Implementation of the Motion Compensation Module for HDTV Video Decoder
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作者 王涛 郑世宝 +1 位作者 邱琳 王峰 《Journal of Shanghai Jiaotong university(Science)》 EI 2006年第1期1-8,共8页
This paper presented a new solution for motion compensation module in the high definition television (HDTV) video decoder. The overall architecture and the design of the major functional units, such as the motion vect... This paper presented a new solution for motion compensation module in the high definition television (HDTV) video decoder. The overall architecture and the design of the major functional units, such as the motion vector decoder, the predictor, and the mixer, were discussed. Based on the exploitation of the special characteristics inherent in the motion compensation algorithm, the motion compensation module and its functional units adopt various novel architectures in order to allow the module to meet real-time constraints. This solution resolves the problem of high hardware costs, low bus efficiency and complex control schemes in conventional designs. 展开更多
关键词 asynchronous macroblock pipelining architecture HDTV video decoder motion compensation module MPEG-2
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