Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,...Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations.展开更多
We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates...We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach.The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths.The proposed architecture supports constraint lengths from 3 to 9,code rates of 1/2,1/3,and 1/4,and fully optional polynomials.The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.展开更多
基金supported in part by the National Key R&D Program(Grant No.2017YFE0121300)in part by the National Natural Science Foundation of China (Grant No. 61501321)+1 种基金in part by Tianjin science and technology program (Grant No. 17ZXRGGX00160)the support of the TEXEO project TEC201680339R funded by the Spanish Ministry of Economy and Competitivity
文摘Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations.
基金Project supported by the Natural Science Foundation of Jiangsu Province,China(No.BK20130156)the Summit of the Six Top Talents Program of Jiangsu Province,China(No.2013-DZXX-027)+1 种基金the Fundamental Research Funds for the Central Universities,China(No.JUSRP51510)the Graduate Student Innovation Program for Universities of Jiangsu Province,China(Nos.KYLX15_1192,KYLX16_0776,and SJLX16_0500)
文摘We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach.The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths.The proposed architecture supports constraint lengths from 3 to 9,code rates of 1/2,1/3,and 1/4,and fully optional polynomials.The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.
