A Novel Time Domain Noise Model for Voltage Controlled Oscillators

This paper describes a novel time domain noise model for voltage controlled oscillators that accurately and efficiently predicts both tuning behavior and phase noise performance. The proposed method is based on device level flicker and thermal noise models that have been developed in Simulink and although the case study is a multiple feedback four delay cell architecture it could easily be extended to any similar topology. The strength of the approach is verified through comparison with post layout simulation results from a commercial simulator and measured results from a 120 nm fabricated prototype chip. Furthermore, the effect of control voltage flicker noise on oscillator output phase noise is also investigated as an example application of the model. Transient simulation based noise analysis has the strong advantage that noise performance of higher level systems such as phase locked loops can be easily determined over a realistic acquisition and locking process yielding more accurate and reliable results.

A Configuration for Realizing Voltage Controlled Floating Inductance and Its Application

A configuration using current feedback amplifiers AD844 and multiplier AD534 has been presented, which is capable of realizing Voltage Controlled Floating Inductance (proportional and in-verse proportional). The application of band pass filter in Figure 4(a), notch filter in Figure 5(a) and Hartley oscillator in Figure 6(a) and simulation result in Figures 4(b)-(d), Figures 5(b)-(d), Figures 6(b)-(d) shows the workability of proposed configuration.

LC型VCO高温特性分析

微波单片集成电路(MMIC)具有噪声性能好、集成度高、驱动能力强的优点。在MMIC工艺下,对压控振荡器(VCO)在高温下的特性表现进行了分析。现有使用负阻振荡原理设计的VCO电路分为负阻电路部分和谐振电路部分,该结构在高温下常产生近端噪声恶化和频率下降的现象,影响VCO的正常工作性能。通过对现有MMICVCO产品的仿真测试和分析,探得了高温下VCO性能改变的原因。

基于变压器磁调谐的双模W波段VCO

提出了一种基于变压器的用于无变容管W波段压控振荡器(VCO)的磁调谐技术。通过控制变压器磁调谐线圈所连接MOS管的开关状态,引入了四个重叠的频率子带。所提出的可切换的六线圈变压器采用40 nm CMOS工艺的顶层厚金属设计,实现了较高的输出频率稳定性和谐振腔品质因数。所采用的技术在对相位噪声的不利影响最小的情况下扩展了调谐范围,实现了无变容管W波段VCO的宽调谐范围和低功耗。所设计的双模W波段VCO输出频率为84.2~107.5 GHz,频率调谐范围大于24%,在1 V电源电压下功耗仅6.1 mW,在10 MHz偏移处的相位噪声为-107.203~-97.875 dBc/Hz。

Locating Sources of Oscillations Induced by Control of Voltage Source Converters Based on Energy Structure and Nonlinearity Detection

The oscillation phenomena associated with the control of voltage source converters(VSCs)are concerning,making it crucial to locate the sources of such oscillations and suppress the oscillations.Therefore,this paper presents a location scheme based on the energy structure and nonlinearity detection.The energy structure,which conforms to the principle of the energy-based method and dissipativity theory,is developed to describe the transient energy flow for VSCs,based on which a defined characteristic quantity is implemented to narrow the scope for locating the sources of oscillations.Moreover,based on the self-sustained oscillation characteristics of VsCs,an index for nonlinearity detection is applied to locate the VSCs that produce the oscillation energy.The combination of the energy structure and nonlinearity detection distinguishes the contribu-tions of different VSCs to the oscillation.The results of a case study implemented by the PSCAD/EMTDC simulation validate theproposed scheme.

应用于5.8 GHz频段雷达的高性能VCO的设计

为满足5.8 GHz频段的多普勒雷达系统应用需要,设计了一种基于HLMC 55 nm射频CMOS工艺的低功耗、低噪声、宽调谐范围压控振荡器(VCO)。该VCO采用了5位电容阵列,实现了4.9 GHz到7.3 GHz共2.4 GHz的宽调谐范围,且通过压控电容偏置方法,使得相邻子带频率重叠范围达到50%以上;为了提高VCO的噪声性能,使用了自行设计的8字电感,EM仿真下电感值为1.04 nH,品质因素Q值为16.8。后仿真结果表明,该VCO在1.2 V电源下工作电流1.5 mA,功耗1.8 mW。该VCO关注低频部分的相位噪声,优化相位噪声在100 Hz偏移处为-12 dBc/Hz,在1 MHz偏移处为-108.6 dBc/Hz,在10 MHz偏移处为-130.3 dBc/Hz。

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply VDD = 1.8 V, the resulting set of performance parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.

A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes

A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.

The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators

By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.

High performance of low voltage controlled ring oscillator with reverse body bias technology

In complementary metal oxide semiconductor （CMOS） nanoscalc technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for critical communication systems with high oscillation frequency. An ideal approach has been presented with substrate biasing technique for reduction of power consumption. The simulation have been completed using cadence virtuoso 45 nm standard CMOS technology at room temperature 27~C with supply voltage Vc^d = 0.7 V. The simulation results suggest that voltage controlled ring oscillator has characterized with efficient low power voltage controlled oscillator （VCO） in term of minimum leakage power （1.23 nW） and maximum oscilla- tion frequency （4.76 GHz） with joint positive channel metal oxide semiconductor and negative channel metal oxide semiconductor （PMOS and NMOS） reverse sub- strate bias technique. PMOS, NMOS and joint reverse body bias techniques have been compared in the presented work.

An efficient PSP-based model for optimized cross-coupled MOSFETs in voltage controlled oscillator

This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design.

CMOS Phase and Quadrature Pulsed Differential Oscillators Coupled through Microstrip Delay-Lines

An innovative solution to design phase and quadrature pulsed coupled oscillators systems through electromagnetic waveguides is described in this paper. Each oscillator is constituted by an LC differential resonator refilled through a couple of current pulse generator circuits. The phase and quadrature coupling between the two differential oscillators is achieved using delayed replicas of generated fundamentals from a resonator as driving signal of pulse generator injecting in the other resonator. The delayed replicas are obtained by microstrip-based delay-lines. A 2.4 - 2.5 GHz VCO has been implemented in a 150 nm RF CMOS process. Simulations showed at 1 MHz offset a phase noise of -139.9 dBc/Hz and a FOM of -189.1 dB.

A micromechanical bridge-shaped voltage-controlled oscillator

A novel micromechanical bridge-shaped voltage-controlled oscillator with high Q value was fabricated. The core of this kind of oscillators is an electrothermally excited and piezoresistively detected micromechanical bridge resonator. Its resonance frequency can be adjusted by changing the DC voltage applied to the Wheatstone bridge. Theoretical analysis and experimental data show that its resonance frequency is linear with the square of the DC voltage. The linearity is better than 0.16% and the adjustable frequency range excels 17.15%.

Wideband CMOS LC VCO design and phase noise analysis

A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors＇ width-length ratios are deduced by a linear time variant （LTV） model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm.

基于改进开关可调电容的宽调谐太赫兹频率源设计

针对太赫兹频率源调谐范围窄的问题,基于普通PMOS可变电容设计了一种改进的开关可调电容,实现了电容变化的单调性,并基于该电容结合衬底调谐方式设计了一种宽调谐范围、高输出功率的压控振荡器(Voltage-controlled oscillator, VCO)。将设计的VCO结合二倍频器实现了一种工作在太赫兹频段的,具有较宽调谐范围及较高输出功率的太赫兹频率源。使用40 nm CMOS工艺设计的太赫兹频率源输出频率为146.3~168.5 GHz,调谐范围14.1%,并同时具有最高1.3 dBm的输出功率,其在10 MHz频偏处的相位噪声最优为-105.52 dBc/Hz。

一种宽带低功耗的VCO设计

以40 nm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺为基础,设计可变电容接入电路的方式,该电路由一组固定的可变大电容与3位开关控制的可变小电容阵列组成,能很好地抑制调谐增益的变化,并且在可变电容两端加入偏置,让其工作在容值变化较为合适的区间,使控制电压对调谐范围的利用率达到最优。测试结果表明,在电源电压为1.1 V的条件下,该压控振荡器的设计功耗为1.155 mW,版图面积仅为0.089 mm2。频率的调谐范围是4.08~5.62 GHz,中心频率在4.8 GHz时的相位噪声为-116.46 dBc/Hz@1 MHz,考虑调谐范围的性能系数(Figure of Merit,FOM)值为-200.03 dBc/Hz,具有良好的综合性能。

应用于TDC电路的低相噪电荷泵锁相环

基于SMIC 0.18μm CMOS工艺实现了一种低相位噪声的四级差分延迟振荡器结构锁相环。通过增加额外的充、放电支路和单位增益放大器优化电荷泵结构,有效减少锁相环电路中的时钟馈通、电荷共享等非理想因素,同时采用重定时结构的反馈回路消除了电路中噪声的积累。测试结果表明,当输入参考频率为40 MHz时,锁相环的输出中心频率在5μs内稳定到960 MHz,相位噪声为-125 dBc/Hz@1 MHz,较好解决了传统锁相环结构由于噪声抑制性能差而无法满足高精度时间-数字转换(Time-to-digital conversion,TDC)电路要求的问题。

基于等效阻抗渐变变压器的宽带压控振荡器

设计了一种基于65 nm CMOS工艺的毫米波宽带压控振荡器(VCO)。分析了应用于宽带VCO的宽带化技术。针对高频相位噪声性能恶化这一问题,提出并设计了一种等效阻抗渐变变压器,以优化VCO高频段相位噪声。该压控振荡器输出信号频率为20.4~40.2 GHz,覆盖24~26 GHz、38~39 GHz两个5G毫米波通信频段。全频带内,相位噪声小于-102 dBc/Hz,品质因子大于180.9 dBc/Hz。

基于相对等效短路比的新能源——柔直送出系统振荡风险评估

新能源基地并网系统面临与电压支撑强度密切相关的振荡稳定性问题,在海量运行方式下,逐一建立精细化模型的稳定性分析过程耗时较长。短路比指标可直观反映新能源并网系统的电压支撑强度和稳定裕度,但现有短路比无法适用于无同步机电源的系统。为此,将短路比概念合理扩展至全电力电子化系统,基于戴维南等效网络来度量新能源-柔直送出系统电压支撑强度,进而提出了能快速评估新能源-柔直送出系统振荡风险的相对等效短路比计算方法,并阐明相对等效短路比能够全面考虑新能源场站发电功率、交流网架结构以及新能源设备变流控制系统等多重因素对振荡稳定性的影响,最后通过算例验证了相对等效短路比评估方法的有效性。

低抖动电荷泵锁相环设计及其Simulink建模仿真

随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。