A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band

In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems applications. For improving the phase noise, filtering technique is used and VCO is designed with TSMC CMOS 0.18 μm technology and the power supply is 1.5 V. The simulation results with advanced design system (ADS) shows that phase noise in 1 MHz offset frequency from the carrier is -122 dBc/Hz and tuning range is 2 to 2.8 GHz. The power consumption of the core is 2.49 mW.

An efficient PSP-based model for optimized cross-coupled MOSFETs in voltage controlled oscillator

This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design.

High performance of low voltage controlled ring oscillator with reverse body bias technology

In complementary metal oxide semiconductor （CMOS） nanoscalc technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for critical communication systems with high oscillation frequency. An ideal approach has been presented with substrate biasing technique for reduction of power consumption. The simulation have been completed using cadence virtuoso 45 nm standard CMOS technology at room temperature 27~C with supply voltage Vc^d = 0.7 V. The simulation results suggest that voltage controlled ring oscillator has characterized with efficient low power voltage controlled oscillator （VCO） in term of minimum leakage power （1.23 nW） and maximum oscilla- tion frequency （4.76 GHz） with joint positive channel metal oxide semiconductor and negative channel metal oxide semiconductor （PMOS and NMOS） reverse sub- strate bias technique. PMOS, NMOS and joint reverse body bias techniques have been compared in the presented work.

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

IC design of low power, wide tuning range VCO in 90 nm CMOS technology

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET（IMOS） varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range（FTR） of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.

8.64-11.62 GHz CMOS VCO and divider in a zero-IF 802.11a/b/g WLAN and Bluetooth application

A fully integrated VCO and divider implemented in SMIC 0.13μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented. The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.1 1 a WLAN in 5.8 GHz band or for 802.1 1b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4, respectively. A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands. The testing results show that the VCO has a phase noise of-113 dBc @ 1 MHz offset from the cartier of 5.5 GHz by dividing VCO output by two and the VCO core consumes 3.72 mW. The figure-of-merit for the tuning-range （FOMT） of the VCO is -192.6 dBc/Hz.

A low power CMOS VCO using inductive-biasing with high performance FoM

A novel voltage-controlled oscillator（VCO） topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using timevarying phase noise theory derives closed-form symbolic formulas for the 1/f^2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 m CMOS technology. Working under a 0.3 V supply voltage with 1.2 m W power consumption, the measured phase noise of the VCO is –119.4 d Bc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an Fo M of 192.5 d Bc/Hz.

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator （VCO） with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS （I-MOS） capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 ×0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6,35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz.

A Ku-band wide-tuning-range high-output-power VCO in InGaP/GaAs HBT technology

A fully integrated Ku-band voltage controlled oscillator （VCO） is presented in an InGaP/GaAs hetero- junction bipolar transistor （HBT） technology. To achieve the wide tuning range （TR）, the VCO employs a Colpitts configuration, and the VCO simultaneously achieves high output power. The implemented VCO demonstrates an oscillation frequency range from 12.82 to 14.97 GHz, a frequency TR of 15.47%, an output power from 0.31 to 6.46 dBm, and a phase noise of -94.9 dBc/Hz at 1 MHz offset from 13.9 GHz center frequency. The VCO con- sumes 52.75 mW from 5 V supply and occupies an area of 0.81 × 0.78 mm2. Finally, the figures-of-merit for VCOs is discussed.

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.

A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers

A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 #m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.

A wideband 0.13μm CMOS LC-VCO for IMT-advanced and UWB applications

This paper presents an LC voltage controlled oscillator（VCO） in a dual-band frequency synthesizer for IMT-advanced and UWB applications.The switched current source,cross-coupled pair and noise filtering technique are adopted in this VCO design to improve the performance of the phase noise,power consumption,voltage amplitude,and tuning range.In order to achieve a wide tuning range,a reconfigurable LC tank with 4 bits switch control is adopted in the core circuit design.The size of the entire chip with pad is 1.11 0.98 mm2.The test results show that the current dissipation of the VCO at UWB and IMT-Advanced band is 3 mA and 4.5 mA in a 1.2 V supply.The tuning range of the designed VCO is 3.86-5.28 GHz and 3.14-3.88 GHz.The phase-noise at 1 MHz frequency offset from a 3.5 GHz and 4.2 GHz carrier is-123 dBc/Hz and-119 dBc/Hz,respectively.

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector（PFD）,and a new feedback structure is utilized in the charge pump（CP） for ultra-low voltage applications.The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power.In addition,several novel design techniques,such as removing the tail current source,are demonstrated to cut down the phase noise.Implemented in the SMIC 0.13μm RF CMOS process and operated at 0.8 V supply voltage,the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz.The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply.The occupied chip area of the PFD and CP is 100×100μm^2.The chip occupies 0.63 mm^2,and draws less than 6.54 mW from a 0.8 V supply.

A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network（WLAN） transceivers.A monolithic LC voltage controlled oscillator（VCO） is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping（MASH）△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector （PFD） frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm^2.

Design of 1.9 GHz RF CMOS VCO

A voltage controlled oscillator （VCO） module is designed, which can be used for the third generation mobile communication （3G） system. The circuit is simulated by spectre radio frequency （RF） by TSMC 0.25 μm CMOS process. During the simulation, the performance parameters of the designed VCO are as follows： tuning range 1.804 GHz-2.039 GHz, phase noise - 136.457 dBc/Hz @1 MHz, - 146.045 dBc/Hz@3 MHz, supply voltage 2.5 V, voltage output rate of 0.8 V-2.6 V, power consumption 25 roW. The layout of the related circuit is drawn by the Virtuoso Layout Editor.

Analysis and Design of an Improved Servo System for Rubidium Atomic Frequency Standard

In this paper, we analyze and design a new type of servo system with noninteger voltage controlled crystal oscillator （VCXO） for rubidium atomic frequency standard （RAFS）, which does not require fractional frequency synthesizer. By the estab- lishment of the loop equations with noises and drifts, we prove that all the components of the loop can affect its performance in- dex, and in which, RAFS long-term frequency stability is mainly determined by frequency multiplier, quantum system, and servo amplifier; the short-term one is mostly decided by VCXO. Owing to the elimination of the frequency synthesizer and its additive mixing unit, we can reduce phase noise and stray of the servo sys- tem, and it is favorable for miniaturizing the RAFS system. In addition, we adopt some targeted optimization measures to im- prove the frequency stability index. The good short-term fre- quency stability index is also validated by the test results.

A low-phase-noise LC-VCO with an enhanced-Q varactor for use in a high-sensitivity GNSS receiver

An LC-VCO with an enhanced quality factor（Q） varactor for use in a high-sensitivity GNSS receiver is presented.An enhanced A-MOS varactor is composed of two accumulation-mode MOS（A-MOS） varactors and two bias voltages,which show the improved Q and linearization capacitance-voltage（C-V） curve.The VCO gain（K_（vco）） is compensated by a digital switched varactors array（DSVA） over entire sub-bands.Based on the characteristics of an A-MOS,the varactor in a DSVA is a high Q fixed capacitor as it is switched off,and a moderate Q tuning varactor when it is switched on,which keeps the maximal Q for the LC-tank.The proposed circuit is fabricated in a 0.18μm 1P6M CMOS process.The measured phase noise is better than -122 dBc/Hz at a 1 MHz offset while the measured tuning range is 58.2%and the variation of K_（VCO） is close to±21%over the whole of the sub-bands and the effective range of the control voltage.The proposed VCO dissipates less than 5.4 mW over the whole operating range from a 1.8 V supply.