IC Implementation of a Programmable CMOS Voltage Reference

A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0. 35μm mixed-signal technology. Measurements demonstrate that the temperature coefficient is ± 36. 3ppm/℃ from 0 to 100℃ when the VID inputs are 11110.As the supply voltage is varied from 2.7 to 5V, the voltage reference varies by about 5mV. The maximum glitch of the transient response is about 20mV at 125kHz. Depending on the state of the five VID inputs,an output voltage between 1.1 and 1.85V is programmed in increments of 25mV.

A Novel CMOS Voltage Reference Based on Threshold Voltage Difference Between p-Type and n-Type MOSFETs

A novel MOS-only voltage reference is presented,which is based on the threshold voltage difference between p-type and n-type MOSFETs. Its precision is improved by the cancellation of the process variation. The reference has been successfully implemented in a Chartered 0.35μm CMOS process. The occupied chip area is 0. 022mm^2. Measurements indicate that without trimming, the average output voltage error is 6mV at room temperature compared with the simulation result. The temperature coefficient is 180ppm/℃ in the worst case in the temperature range of 0 to 100℃ ,and the line regulation is ± 1.1%. The reference is applied in an adaptive power MOSFET driver.

A CMOS Voltage Reference Based on V_(GS) and ΔV_(GS) in the Weak Inversion Region

A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJTs） are used. The proposed voltage reference uses a current-mode topology by summing a PTAT current and a CTAT current into a re- sistor to generate the required reference voltage. It can also provide more than one reference voltage output, which is quite suitable for systems requiring many different reference voltages simultaneously. The occupied chip area is 0. 023mm^-2 . The operation supply voltage is from 2.5 to 6V, and the maximum supply current is 8.25μA. The designed three different out- puts are respectively about 203mV, 1.0V, and 2.05V at room temperature when the supply voltage is 4V. The circuit achieves a temperature coefficient of 31ppm/℃ in the temperature range of 0 to 100℃ and an average line regulation of ± 0. 203%/V. The voltage reference has been successfully applied in a white LED backlight driver chip.

Sub-1V CMOS Voltage Reference Based on Weighted V_(gs)

We propose a voltage reference based on the weighted difference between the gate-source voltages of an nMOS and a pMOS operating in their saturation regions. No diodes or parasitic bipolar transistors are used, The circuit is simulated and fabricated with SMIC 0.18μm mixed-signal technology,and our measurements demonstrate that its temperature coefficient is 44ppm/℃ and its PSRR is - 46dB, It works well when Vdd is above 650mV. The active area of the circuit is about 0.05mm^2.

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.

A band-gap voltage reference for interface circuit of microsensor

A high performance CMOS band-gap voltage reference circuit that can be used in interface integrated circuit of microsensor and compatible with 0. 6 μm ( double poly) mix process is proposed in this paper. The circuit can be employed in the range of 1. 8 - 8 V and carry out the first-order PTAT ( proportional to absolute temperature) temperature compensation. Through using a two-stage op-amp with a NMOS input pair as a negative feedback op-amp,the PSRR ( power supply rejection ratio) of the entire circuit is increased,and the temperature coefficient of reference voltage is decreased. Results from HSPICE simulation show that the PSRR is - 72. 76 dB in the condition of low-frequency,the temperature coefficient is 2. 4 × 10 -6 in the temperature range from - 10 ℃ to 90 ℃ and the power dissipation is only 14 μW when the supply voltage is 1. 8 V.

A Super Performance Bandgap Voltage Reference with Adjustable Output for DC-DC Converter

This paper presents a super performance bandgap voltage reference for DC-DC converter with adjustable output. it generates a wide range of voltage reference ranging from sub- 1V to 1,221 7 V and has a low temperature coefficient of 2.3 × 10 ^5/K over the temperature variation using the current feedback and resistive subdivision. In addition, the power supply rejection ration of the proposed bandgap voltage reference is 78 dB. When supply voltage varies from 2.5 V to 6 V, output VREF is 1,221 685±0.055 mV.

A 150-nA 13.4-ppm/℃switched-capacitor CMOS sub-bandgap voltage reference

A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 035-μm 3.3-V/5-V dual gate mixed-signal CMOS process.The proposed circuit generates a precise sub-bandgap voltage of 1 V.The temperature coefficient of the output voltage is 13.4 ppm/℃with the temperature varying from -20 to 80℃.The proposed circuit operates properly with the supply voltage down to 1.3 V,and consumes 150 nA at room temperature.The line regulation is 0.27%/V.The power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB,respectively.The chip area is 0.2 mm2.

A new curvature compensation technique for CMOS voltage reference using |V_(GS)| and △V_(BE)

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage｜VGS｜p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages｜VGS｜n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages △VBE of bipolar junction transistors （BJTs）. The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 pprrd /℃ without trimming, over a temperature range from -40 to 120℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio （PSRR） is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2.

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

A novel current-mode voltage reference circuit which is capable of generating sub- 1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature com- pensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to re- duce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × ll0μm2

Novel high-PSRR high-order curvature-compensated bandgap voltage reference

This paper proposes a novel high-power supply rejection ratio（high-PSRR） high-order curvature-compensated CMOS bandgap voltage reference（BGR） in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvaturecorrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T^（1.5） current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42x10^（-6）′ /℃ from - 55 ℃ to 125 ℃ with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of - 123.51 dB, - 123.52 dB, - 88.5 dB and - 50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.

An extremely low power voltage reference with high PSRR for power-aware ASICs

An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio （PSRR） and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.

A Piecewise-Linear Compensated Bandgap Reference

A bandgap voltage reference is presented with a piecewise linear compensating circuit in order to reduce the temperature coefficient.The basic principle is to divide the whole operating temperature range into some sub ranges.At different temperature sub ranges the bandgap reference can be compensated by different linear functions.Since the temperature sub range is much narrower than the whole range,the compensation error can be reduced significantly.Theoretically,the precision can be improved unlimitedly if the sub ranges are narrow enough.In the given example,with only three temperature sub ranges,the temperature coefficient of a conventional bandgap reference drops from 1 5×10 -5 /℃ to 2×10 -6 /℃ over the -40℃ to 120℃ temperature range.

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.

Low voltage bandgap reference with closed loop curvature compensation

A new low-voltage CMOS bandgap reference （BGR） that achieves high temperature stability is proposed. It feeds back the output voltage to the curvature compensation circuit that constitutes a closed loop circuit to cancel the logarithmic term of voltage VBE. Meanwhile a low voltage amplifier with the 0.5 μm low threshold technology is designed for the BGR. A high temperature stability BGR circuit is fabricated in the CSMC 0.5μm CMOS technology. The measured result shows that the BGR can operate down to 1 V, while the temperature coefficient and line regulation are only 9 ppm/℃ and 1.2 mV/V, respectively.

A reference voltage in capacitor–resister hybrid SAR ADC for front-end readout system of CZT detector

An on-chip reference voltage has been designed in capacitor-resister hybrid SAR ADC for CZT detec- tor with the TSMC 0.35 μm 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power con- sumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80 ℃, the temperature coefficient is 12.2 ppm/℃. The PSRR was -70 dB @ 100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449 × 614μm2. The total power consumption is only 1.092 mW.

Negative voltage bandgap reference with multilevel curvature compensation technique

A novel high-order curvature compensation negative voltage bandgap reference （NBGR） based on a novel multilevel compensation technique is introduced. Employing an exponential curvature compensation （ECC） term with many high order terms in itself, in a lower temperature range （TR） and a multilevel curvature compen- sation （MLCC） term in a higher TR, a flattened and better effect of curvature compensation over the TR of 165℃ （--40 to 125 ℃） is realised. The MLCC circuit adds two convex curves by using two sub-threshold operated NMOS. The proposed NBGR implemented in the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 #m BCD technology demonstrates an accurate voltage of-1.183 V with a temperature coefficient （TC） as low as 2.45 ppm/℃over the TR of 165℃ at a -5.0 V power supply; the line regulation is 3 mV/V from a -5 to -2 V supply voltage. The active area of the presented NBGR is 370×180 μm2.

A low drift curvature-compensated bandgap reference with trimming resistive circuit

A low temperature drift curvature-compensated complementary metal oxide semiconductor (CMOS) bandgap ref-erence is proposed.A dual-differential-pair amplifier was employed to add compensation with a high-order term of TlnT (T is the thermodynamic temperature) to the traditional 1st-order compensated bandgap.To reduce the offset of the amplifier and noise of the bandgap reference,input differential metal oxide semiconductor field-effect transistors (MOSFETs) of large size were used in the amplifier and to keep a low quiescent current,these MOSFETs all work in weak inversion.The voltage reference's temperature curvature has been further corrected by trimming a switched resistor network.The circuit delivers an output voltage of 3 V with a low dropout regulator (LDO).The chip was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC)'s 0.35-μm CMOS process,and the temperature coefficient (TC) was measured to be only 2.1×10 6/°C over the temperature range of 40-125 °C after trimming.The power supply rejection (PSR) was 100 dB @ DC and the noise was 42 μV (rms) from 0.1 to 10 Hz.

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations.In addition,an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed.Based on the CSMC 0.5μm 20 V BCD process,the designed circuit is implemented;the active die area is 0.17×0.20 mm;. Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from -40 to 150℃,the power supply rejection ratio is -98.2 dB,the line regulation is 0.3 mV/V,and the power consumption is only 0.38 mW.The proposed bandgap voltage reference has good characteristics such as small area,low power consumption, good temperature stability,high power supply rejection ratio,as well as low line regulation.This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog,digital and mixed systems.

Design and implementation of an ultra-low power passive UHF RFID tag

This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18μm CMOS process with a die size of 800×800μm;. Measurement results show that the total power consumption of the tag chip is only 7.4μW with a sensitivity of -12 dBm.