Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm.The data-level parallelism is improved by instructions to dynamically configure the multi-core computing units.Simultaneously,an intelligent adjustment strategy based on a programmable wake-up controller(WuC)is designed so that the computing mode,operating voltage,and frequency of the QC-LDPC algorithm can be adjusted.This adjustment can improve the computing efficiency of the processor.The QC-LDPC processors are verified on the Xilinx ZCU102 field programmable gate array(FPGA)board and the computing efficiency is measured.The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency.The maximum efficiency can reach up to 12.18 Gbit/(s·W),which is more flexible than existing state-of-the-art processors for QC-LDPC.

A survey and measurement study of GPU DVFS on energy conservation

Energy efficiency has become one of the top design criteria for current computing systems. The Dynamic Voltage and Frequency Scaling （DVFS） has been widely adopted by laptop computers, servers, and mobile devices to conserve energy, while the GPU DVFS is still at a certain early age. This paper aims at exploring the impact of GPU DVFS on the application performance and power consumption, and furthermore, on energy conservation. We survey the state-of-the-art GPU DVFS characterizations, and then summarize recent research works on GPU power and performance models. We also conduct real GPU DVFS experiments on NVIDIA Fermi and Maxwell GPUs. According to our experimental results, GPU DVFS has significant potential for energy saving. The effect of scaling core voltage/frequency and memory voltage/frequency depends on not only the GPLI architectures, but also the characteristic of GPU applications.

Optimization of synchronized frequency and voltage control for a distributed generation system using the Black Widow Optimization algorithm

A distributed generation network could be a hybrid power system that includes wind-diesel power generation based on induction generators(IGs)and synchronous generators(SGs).The main advantage of these systems is the possibility of using renewable energy in their structures.The most important challenge is to design the voltage-control loop with the frequency-control loop to obtain optimal responses for voltage and frequency deviations.In this work,the voltage-control loop is designed by an automatic voltage regulator.A linear model of the hybrid system has also been developed with coordinated voltage and frequency control.Dynamic frequency response and voltage deviations are compared for different load disturbances and different reactive loads.The gains of the SG and the static volt-ampere reactive compensator(SVC)controllers in the IG terminal are calculated using the Black Widow Optimization(BWO)algorithm to insure low frequency and voltage deviations.The BWO optimization algorithm is one of the newest and most powerful optimization methods to have been introduced so far.The results showed that the BWO algorithm has a good speed in solving the proposed objective function.A 22%improvement in time adjustment was observed in the use of an optimal SVC.Also,an 18%improvement was observed in the transitory values.

Ant Lion Algorithm for Optimized Controller Gains for Power Quality Enrichment of Off-grid Wind Power Harnessing Units

The proposed system uses an algorithm that works on the admittance of the system,for estimating the reference values of generated currents for an off-grid wind power harnessing unit(WPHU).The controller controls the voltage and maintains the frequency within the limits while working with both linear and nonlinear loads for varying wind speeds.The admittance algorithm is simple and easy to implement and works very efficiently to generate the triggering signals for the controller of the WPHU.The wind power harnessing unit comprising of a squirrel cage induction generator,a star-delta transformer,a battery storage system and the control unit are modeled using Matlab/Simulink R2019.An isolated transformer with a star-delta configuration connects the load and the generator circuit with the controller to reduce the dc bus voltage and mitigate current in the neutral line.The response of the system during the dynamic loading depends on the best possible compensator proportional-integral(PI)gains.The antlion optimization algorithm is compared with particle swarm optimization and grey wolf optimization and is found to have the advantages of good convergence,high efficiency and fast calculating speed.It is therefore used to extract the optimal values of frequency and voltage PI gains.The simulation results of the control algorithm for the WPHU are validated in a real-time environment in a dSpace1104 laboratory set up.This algorithm is proven to have a quick response,maintain the required frequency,suppress the current harmonics,regulate voltage,help in balancing the load and compensating for the neutral current.

Energy Efficient Block-Partitioned Multicore Processors for Parallel Applications

Due to the increasing power consumption in modern computing systems, energy management has become an important research area in the last decade. Recently, multicore has emerged to be an energy efficient architecture that exploits parallelisms in modern applications. However, as the number of cores on a single chip continues to increase, it has been a grand challenge on how to effectively manage the energy efficiency of multicore-based systems. In this paper, based on the voltage island and dynamic voltage and frequency scaling （DVFS） techniques, we investigate the energy efficiency of block-partitioned multieore processors, where cores are grouped into blocks with the cores on one block sharing a DVFS- enabled power supply. Depending on the number of cores on each block, we study both symmetric and asymmetric block configurations. We develop a system-level power model （which can support various power management techniques） and derive both block- and system-wide energy-efficient frequencies for systems with block-partitioned multieore processors. Based on the power model, we prove that, for embarrassingly parallel applications, having all cores on a single block can achieve the same energy savings as that of the individual block configuration （where each core forms a single block and has its own power supply）. However, for applications with limited degrees of parallelism, we show the superiority of the buddy-asymmetric block configuration, where the number of required blocks （and power supplies） is logarithmically related to the number of cores on the chip, in that it can achieve the same amount of energy savings as that of the individual block configuration. The energy efficiency of different block configurations is further evaluated through extensive simulations with both synthetic as well as a real life application.