An accurate 1.08GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process.A new convenient method of calculating oscillator period is presented.With this period calculation tech...An accurate 1.08GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process.A new convenient method of calculating oscillator period is presented.With this period calculation technique,the frequency tuning curves agree well with the experiment.At a 3.3V supply,the LC-VCO measures a phase noise of -82.2dBc/Hz at a 10kHz frequency offset while dissipating 3.1mA current.The chip size is 0.86mm×0.82mm.展开更多
A monolithic 10GHz LC voltage-controlled oscillator （VCO） is implemented in standard 0.25μm CMOS technology. The VCO adopts an optimized symmetric circular inductor with center-tap, an accumulation-mode MOS （A-MOS...A monolithic 10GHz LC voltage-controlled oscillator （VCO） is implemented in standard 0.25μm CMOS technology. The VCO adopts an optimized symmetric circular inductor with center-tap, an accumulation-mode MOS （A-MOS） varactor in series with a passive metal-isolator-metal capacitor （MIM-CAP） and a tail current source with an LC filter to operate with high-frequency and low-noise resulting in - 103.2dBc/Hz at 1MHz offset from carrier frequency of 10.2GHz and approximately 11.5% tuning range. With a 3.3V supply voltage, the core circuit consumes 9.9mW. The chip area is 0.67mm × 0.58mm.展开更多
In the presence of Gaussian white noise,we study the properties of voltage-controlled oscillator neuronmodel and discuss the effects of the additive and multiplicative noise.It is found that the additive noise can acc...In the presence of Gaussian white noise,we study the properties of voltage-controlled oscillator neuronmodel and discuss the effects of the additive and multiplicative noise.It is found that the additive noise can accelerate andcounterwork the firing of neuron,which depends on the value of central frequency of neuron itself,while multiplicativenoise can induce the continuous change or mutation of membrane potential.展开更多
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
A new method of synthesizing 1GHz based on a 0 5μm CMOS D LL is proposed,which can synthesize frequency with simple logic and amplifiers.T he designed frequency synthesizer consists of a DLL (Delay-Locked Loop) and...A new method of synthesizing 1GHz based on a 0 5μm CMOS D LL is proposed,which can synthesize frequency with simple logic and amplifiers.T he designed frequency synthesizer consists of a DLL (Delay-Locked Loop) and a b uilding block of synthesizing logic.The reference frequency input into this freq uency synthesizer is 25MHz and the synthesized frequency is 1GHz.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
A virtual cathode oscillator （VCO） with a resonant cavity is presented and investigated numerically and theoretically, and its efficiency and stability are enhanced. An equivalent circuit method is introduced to ana...A virtual cathode oscillator （VCO） with a resonant cavity is presented and investigated numerically and theoretically, and its efficiency and stability are enhanced. An equivalent circuit method is introduced to analyze the resonant cavity com- posed of anode foil and feedback annulus, and a theoretical expression for the fundamental mode frequency of the resonant cavity is given. The VCO is investigated in detail with a particle-in-cell method. We obtain the microwave frequencies from simulation, theoretical expression, and relative references, and draw three important conclusions. First, the microwave fre- quency is a constant when the diode voltage is changed from 588 kV to 717 kV. Second, the fluctuation of the microwave frequency is very small when the AK gap is changed from 1.2 cm to 1.6 cm. Third, the microwave frequency agrees with the theoretical result. The relative error, which is calculated according to the theoretical and simulation frequencies, is only 1.7%.展开更多
A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to ex...A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors＇ width-length ratios are deduced by a linear time variant （LTV） model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm.展开更多
The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to...The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.展开更多
文摘An accurate 1.08GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process.A new convenient method of calculating oscillator period is presented.With this period calculation technique,the frequency tuning curves agree well with the experiment.At a 3.3V supply,the LC-VCO measures a phase noise of -82.2dBc/Hz at a 10kHz frequency offset while dissipating 3.1mA current.The chip size is 0.86mm×0.82mm.
文摘A monolithic 10GHz LC voltage-controlled oscillator （VCO） is implemented in standard 0.25μm CMOS technology. The VCO adopts an optimized symmetric circular inductor with center-tap, an accumulation-mode MOS （A-MOS） varactor in series with a passive metal-isolator-metal capacitor （MIM-CAP） and a tail current source with an LC filter to operate with high-frequency and low-noise resulting in - 103.2dBc/Hz at 1MHz offset from carrier frequency of 10.2GHz and approximately 11.5% tuning range. With a 3.3V supply voltage, the core circuit consumes 9.9mW. The chip area is 0.67mm × 0.58mm.
基金National Natural Science Foundation of China under Grant No.30600122Natural Science Foundation of Guangdong Province of China under Grant No.06025073the Natural Science Foundation of South China University of Technology under Grant No.B14-E5050200
文摘In the presence of Gaussian white noise,we study the properties of voltage-controlled oscillator neuronmodel and discuss the effects of the additive and multiplicative noise.It is found that the additive noise can accelerate andcounterwork the firing of neuron,which depends on the value of central frequency of neuron itself,while multiplicativenoise can induce the continuous change or mutation of membrane potential.
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
文摘A new method of synthesizing 1GHz based on a 0 5μm CMOS D LL is proposed,which can synthesize frequency with simple logic and amplifiers.T he designed frequency synthesizer consists of a DLL (Delay-Locked Loop) and a b uilding block of synthesizing logic.The reference frequency input into this freq uency synthesizer is 25MHz and the synthesized frequency is 1GHz.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
基金supported by the National Natural Science Foundation of China(Grant No.11075210)the Postdoctoral Science Foundation of China(GrantNo.201104761)
文摘A virtual cathode oscillator （VCO） with a resonant cavity is presented and investigated numerically and theoretically, and its efficiency and stability are enhanced. An equivalent circuit method is introduced to analyze the resonant cavity com- posed of anode foil and feedback annulus, and a theoretical expression for the fundamental mode frequency of the resonant cavity is given. The VCO is investigated in detail with a particle-in-cell method. We obtain the microwave frequencies from simulation, theoretical expression, and relative references, and draw three important conclusions. First, the microwave fre- quency is a constant when the diode voltage is changed from 588 kV to 717 kV. Second, the fluctuation of the microwave frequency is very small when the AK gap is changed from 1.2 cm to 1.6 cm. Third, the microwave frequency agrees with the theoretical result. The relative error, which is calculated according to the theoretical and simulation frequencies, is only 1.7%.
文摘A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors＇ width-length ratios are deduced by a linear time variant （LTV） model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm.
文摘The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.
