A single-ended wideband reconfigurable receiver front-end for multi-mode multi-standard applications in 0.18μm CMOS

This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

A fully integrated multi-mode multi-band directed-conversion radio frequency （RF） receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented. The front-end employs direct-conversion design, and consists of two differential tunable low noise amplifiers （LNA）, a quadrature mixer, and two intermediate frequency （IF） amplifiers. The two independent tunable LNAs are used to cover all the four frequency bands, achieving sufficient low noise and high gain performance with low power consumption. Switched capacitor arrays perform a resonant frequency point calibration for the LNAs. The two LNAs are combined at the driver stage of the mixer, which employs a folded double balanced Gilbert structure, and utilizes PMOS transistors as local oscillator （LO） switches to reduce flicker noise. The front-end has three gain modes to obtain a higher dynamic range. Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface （SPI） module. The front- end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm2. The measured double- sideband （DSB） noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.

Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.

A 400 MHz Low Noise Amplifier at Cryogenic Temperature for Superconductor Filter System

A cryogenic low noise amplifier （LNA） using Agilent high electron mobility transistor （HEMT） for 380 MHzto 480 MHz is designed and fabricated, and the excellent cryogenic performance in superconducting receiver front-end for communication system is achieved. A special input impedance matching topology is implemented to provide low noise figure （NF） and good input matching in this cryogenic LNA design. The measurement results show that the NF is within 0.25 dB from the minimum NF of a single transistor, the power gain is above 20 dB, the flatness is within 1 dB, and the maximum input return loss is lower than -20 dB in bandwidth.

Quad-channel broadband compact multi-antenna GNSS down-converter for high-reliability navigation

A high-reliability broadband high-linearity down-converter for multi-antenna global navigation satellite system(GNSS)receiver is presented in this paper.Based on direction-of-arrival estimation,the multi-antenna GNSS receiver can separate the GNSS signals from the interfering signals and suppress harmful broadband radio frequency interferences.To drive the off-chip 50Ω2 resistive load and meet the stringent requirements of linearity,a quad-channel down-converter with a broadband common-gate low-noise transcon-ductance amplifier,current-driven passive mixer and novel bridge mode transimpedance driving amplifier have been proposed to contruct the multi-antenna recelver.The operating frequency of this down-converter is from 1.15 to 1.65 GHz,covering all bands for global positioning system(GPS),Beidou navigation satellite system(BDS),global navigation satellite system(GLONASS)and Galileo.The measured results show that the proposed quad-channel down-converter achieves+38 dBm output 3rd order intercept point(OIP3)and+17 dBm OP1dB(output-referred 1 dB compression point),9.5 dB to 12.9 dB noise figure(NF)across the variable gain of 10 dB to 27 dB and approximately 47 dB channel isolation.