To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were iden...To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.展开更多
A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer a...A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer and interconnections are built without an additional transformer chip,and the converter only has 2 dies:a transmitter(TX)chip and a receiver(RX)chip.The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density.Moreover,the transformer built by the RDLs achieves a high quality factor(Q)and high coupling factor(k),and the efficiency of the converter is thus improved.The TX and RX chips were implemented in a 0.18μm Biopolar CMOS DMOS(BCD)process and embedded in a compact package with a size of 5 mm×5 mm.With an output capacitance of 10μF,the converter achieves a peak efficiency of 46.5%at 0.3 W output power and a maximum delivery power of 1.25 W,achieving a maximum power density of 50 mW/mm2.展开更多
本文对扇出型晶圆级封装(Fan out Wafer Level Package,FOWLP)组装工艺的热可靠性进行仿真评价,对关键技术及失效机理进行分析,针对某款基于该项技术的典型封装结构,建立其1/4结构有限元仿真模型,并对在典型军用温度循环条件下的热可靠...本文对扇出型晶圆级封装(Fan out Wafer Level Package,FOWLP)组装工艺的热可靠性进行仿真评价,对关键技术及失效机理进行分析,针对某款基于该项技术的典型封装结构,建立其1/4结构有限元仿真模型,并对在典型军用温度循环条件下的热可靠性进行仿真分析。通过分析FOWLP关键结构在典型航天器用热循环条件下的应力及位移情况,确定了可能引起扇出型晶圆级封装失效的可靠性薄弱点。展开更多
基金Projects(51475072,51171036)supported by the National Natural Science Foundation of China
文摘To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
基金supported in part by the National Natural Science Foundation of China(62104220)in part by the National Key Research and Development Program of China(2019YFB2204800).
文摘A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer and interconnections are built without an additional transformer chip,and the converter only has 2 dies:a transmitter(TX)chip and a receiver(RX)chip.The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density.Moreover,the transformer built by the RDLs achieves a high quality factor(Q)and high coupling factor(k),and the efficiency of the converter is thus improved.The TX and RX chips were implemented in a 0.18μm Biopolar CMOS DMOS(BCD)process and embedded in a compact package with a size of 5 mm×5 mm.With an output capacitance of 10μF,the converter achieves a peak efficiency of 46.5%at 0.3 W output power and a maximum delivery power of 1.25 W,achieving a maximum power density of 50 mW/mm2.
文摘本文对扇出型晶圆级封装(Fan out Wafer Level Package,FOWLP)组装工艺的热可靠性进行仿真评价,对关键技术及失效机理进行分析,针对某款基于该项技术的典型封装结构,建立其1/4结构有限元仿真模型,并对在典型军用温度循环条件下的热可靠性进行仿真分析。通过分析FOWLP关键结构在典型航天器用热循环条件下的应力及位移情况,确定了可能引起扇出型晶圆级封装失效的可靠性薄弱点。
