CMOS-compatible RF/microwave devices,such as filters and amplifiers,have been widely used in wireless communication systems.However,secondary-electron emission phenomena often occur in RF/microwave devices based on si...CMOS-compatible RF/microwave devices,such as filters and amplifiers,have been widely used in wireless communication systems.However,secondary-electron emission phenomena often occur in RF/microwave devices based on silicon(Si)wafers,especially in the high-frequency range.In this paper,we have studied the major factors that influence the secondary-electron yield(SEY)in commercial Si wafers with different doping concentrations.We show that the SEY is suppressed as the doping concentration increases,corresponding to a relatively short effective escape depthλ.Meanwhile,the reduced narrow band gap is beneficial in suppressing the SEY,in which the absence of a shallow energy band below the conduction band will easily capture electrons,as revealed by first-principles calculations.Thus,the new physical mechanism combined with the effective escape depth and band gap can provide useful guidance for the design of integrated RF/microwave devices based on Si wafers.展开更多
The defect detection of wafers is an important part of semiconductor manufacturing.The wafer defect map formed from the defects can be used to trace back the problems in the production process and make improvements in...The defect detection of wafers is an important part of semiconductor manufacturing.The wafer defect map formed from the defects can be used to trace back the problems in the production process and make improvements in the yield of wafer manufacturing.Therefore,for the pattern recognition of wafer defects,this paper uses an improved ResNet convolutional neural network for automatic pattern recognition of seven common wafer defects.On the basis of the original ResNet,the squeeze-and-excitation(SE)attention mechanism is embedded into the network,through which the feature extraction ability of the network can be improved,key features can be found,and useless features can be suppressed.In addition,the residual structure is improved,and the depth separable convolution is added to replace the traditional convolution to reduce the computational and parametric quantities of the network.In addition,the network structure is improved and the activation function is changed.Comprehensive experiments show that the precision of the improved ResNet in this paper reaches 98.5%,while the number of parameters is greatly reduced compared with the original model,and has well results compared with the common convolutional neural network.Comprehensively,the method in this paper can be very good for pattern recognition of common wafer defect types,and has certain application value.展开更多
Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines.During the wafer testing stage,deep learning methods are widely used in wafer defect detection ...Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines.During the wafer testing stage,deep learning methods are widely used in wafer defect detection due to their powerful feature extraction capa-bilities.However,most of the current wafer defect patterns classification models have high complexity and slow detection speed,which are difficult to apply in the actual wafer production process.In addition,there is a data imbalance in the wafer dataset that seriously affects the training results of the model.To reduce the complexity of the deep model without affecting the wafer feature expression,this paper adjusts the structure of the dense block in the PeleeNet network and proposes a lightweight network WM‐PeleeNet based on the PeleeNet module.In addition,to reduce the impact of data imbalance on model training,this paper proposes a wafer data augmentation method based on a convolutional autoencoder by adding random Gaussian noise to the hidden layer.The method proposed in this paper has an average accuracy of 95.4%on the WM‐811K wafer dataset with only 173.643 KB of the parameters and 316.194 M of FLOPs,and takes only 22.99 s to detect 1000 wafer pictures.Compared with the original PeleeNet network without optimization,the number of parameters and FLOPs are reduced by 92.68%and 58.85%,respectively.Data augmentation on the minority class wafer map improves the average classification accuracy by 1.8%on the WM‐811K dataset.At the same time,the recognition accuracy of minority classes such as Scratch pattern and Donut pattern are significantly improved.展开更多
Recently,machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductormanufacturing.The existing approaches used in the wafer map pattern clas...Recently,machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductormanufacturing.The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features.This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns.First,the number of defects during the actual process may be limited.Therefore,insufficient data are generated using convolutional auto-encoder(CAE),and the expanded data are verified using the evaluation technique of structural similarity index measure(SSIM).After extracting handcrafted features,a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction.Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns,the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.展开更多
The process of wafer polishing is known to be highly demanding,and even small deviations in the processing parameters can have a significant impact on the quality of the wafers obtained.During the process of wafer pol...The process of wafer polishing is known to be highly demanding,and even small deviations in the processing parameters can have a significant impact on the quality of the wafers obtained.During the process of wafer polishing,maintaining a constant pressure value applied by the polishing head is essential to achieve the desired flatness of the wafer.The accuracy of the downward pressure output by the polishing head is a crucial factor in producing flat wafers.In this paper,the uncertainty component of downward pressure is calculated and its measurement uncertainty is evaluated,and a method for calculating downward pressure uncertainty traceable to international basic unit is established.Therefore,the reliability of double side polishing machine has been significantly improved.展开更多
Nanogrinding of SiC wafers with high flatness and low subsurface damage was proposed and nanogrinding experiments were carried out on an ultra precision grinding machine with fine diamond wheels. Experimental results ...Nanogrinding of SiC wafers with high flatness and low subsurface damage was proposed and nanogrinding experiments were carried out on an ultra precision grinding machine with fine diamond wheels. Experimental results show that nanogrinding can produce flatness less than 1.0μm and a surface roughness Ra of 0.42nm. It is found that nanogrinding is capable of producing much flatter SiC wafers with a lower damage than double side lapping and mechanical polishing in much less time and it can replace double side lapping and mechanical polishing and reduce the removal amount of chemical mechanical polishing.展开更多
基金Project supported by the Administration of Science,Technology and Industry of National Defense of China (Grant No.HTKJ2021KL504001)the National Natural Science Foundation of China (Grant Nos.12004297 and 12174364)+3 种基金the China Postdoctoral Science Foundation (Grant No.2022M712507)the Fundamental Research Funds for the Central Universities (Grant No.xzy01202003)the National 111 Project of China (Grant No.B14040)the support from the Instrument Analysis Center of Xi’an Jiaotong University。
文摘CMOS-compatible RF/microwave devices,such as filters and amplifiers,have been widely used in wireless communication systems.However,secondary-electron emission phenomena often occur in RF/microwave devices based on silicon(Si)wafers,especially in the high-frequency range.In this paper,we have studied the major factors that influence the secondary-electron yield(SEY)in commercial Si wafers with different doping concentrations.We show that the SEY is suppressed as the doping concentration increases,corresponding to a relatively short effective escape depthλ.Meanwhile,the reduced narrow band gap is beneficial in suppressing the SEY,in which the absence of a shallow energy band below the conduction band will easily capture electrons,as revealed by first-principles calculations.Thus,the new physical mechanism combined with the effective escape depth and band gap can provide useful guidance for the design of integrated RF/microwave devices based on Si wafers.
基金supported by the 2021 Annual Scientific Research Funding Project of Liaoning Pro-vincial Department of Education(Nos.LJKZ0535,LJKZ0526)the Natural Science Foundation of Liaoning Province(No.2021-MS-300)。
文摘The defect detection of wafers is an important part of semiconductor manufacturing.The wafer defect map formed from the defects can be used to trace back the problems in the production process and make improvements in the yield of wafer manufacturing.Therefore,for the pattern recognition of wafer defects,this paper uses an improved ResNet convolutional neural network for automatic pattern recognition of seven common wafer defects.On the basis of the original ResNet,the squeeze-and-excitation(SE)attention mechanism is embedded into the network,through which the feature extraction ability of the network can be improved,key features can be found,and useless features can be suppressed.In addition,the residual structure is improved,and the depth separable convolution is added to replace the traditional convolution to reduce the computational and parametric quantities of the network.In addition,the network structure is improved and the activation function is changed.Comprehensive experiments show that the precision of the improved ResNet in this paper reaches 98.5%,while the number of parameters is greatly reduced compared with the original model,and has well results compared with the common convolutional neural network.Comprehensively,the method in this paper can be very good for pattern recognition of common wafer defect types,and has certain application value.
基金supported by a project jointly funded by the Beijing Municipal Education Commission and Municipal Natural Science Foundation under grant KZ202010005004.
文摘Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines.During the wafer testing stage,deep learning methods are widely used in wafer defect detection due to their powerful feature extraction capa-bilities.However,most of the current wafer defect patterns classification models have high complexity and slow detection speed,which are difficult to apply in the actual wafer production process.In addition,there is a data imbalance in the wafer dataset that seriously affects the training results of the model.To reduce the complexity of the deep model without affecting the wafer feature expression,this paper adjusts the structure of the dense block in the PeleeNet network and proposes a lightweight network WM‐PeleeNet based on the PeleeNet module.In addition,to reduce the impact of data imbalance on model training,this paper proposes a wafer data augmentation method based on a convolutional autoencoder by adding random Gaussian noise to the hidden layer.The method proposed in this paper has an average accuracy of 95.4%on the WM‐811K wafer dataset with only 173.643 KB of the parameters and 316.194 M of FLOPs,and takes only 22.99 s to detect 1000 wafer pictures.Compared with the original PeleeNet network without optimization,the number of parameters and FLOPs are reduced by 92.68%and 58.85%,respectively.Data augmentation on the minority class wafer map improves the average classification accuracy by 1.8%on the WM‐811K dataset.At the same time,the recognition accuracy of minority classes such as Scratch pattern and Donut pattern are significantly improved.
基金the National Research Foundation of Korea(NRF)grant funded by the Korea government(MSIT)(No.NRF-2021R1A5A8033165)the“Human Resources Program in Energy Technology”of the Korea Institute of Energy Technology Evaluation and Planning(KETEP)and was granted financial resources from the Ministry of Trade,Industry&Energy,Republic of Korea(No.20214000000200).
文摘Recently,machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductormanufacturing.The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features.This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns.First,the number of defects during the actual process may be limited.Therefore,insufficient data are generated using convolutional auto-encoder(CAE),and the expanded data are verified using the evaluation technique of structural similarity index measure(SSIM).After extracting handcrafted features,a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction.Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns,the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.
文摘The process of wafer polishing is known to be highly demanding,and even small deviations in the processing parameters can have a significant impact on the quality of the wafers obtained.During the process of wafer polishing,maintaining a constant pressure value applied by the polishing head is essential to achieve the desired flatness of the wafer.The accuracy of the downward pressure output by the polishing head is a crucial factor in producing flat wafers.In this paper,the uncertainty component of downward pressure is calculated and its measurement uncertainty is evaluated,and a method for calculating downward pressure uncertainty traceable to international basic unit is established.Therefore,the reliability of double side polishing machine has been significantly improved.
基金Project (50975040) supported by the National Natural Science Foundation of China
文摘Nanogrinding of SiC wafers with high flatness and low subsurface damage was proposed and nanogrinding experiments were carried out on an ultra precision grinding machine with fine diamond wheels. Experimental results show that nanogrinding can produce flatness less than 1.0μm and a surface roughness Ra of 0.42nm. It is found that nanogrinding is capable of producing much flatter SiC wafers with a lower damage than double side lapping and mechanical polishing in much less time and it can replace double side lapping and mechanical polishing and reduce the removal amount of chemical mechanical polishing.
