To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were iden...To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.展开更多
A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding param...A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.展开更多
基金Projects(51475072,51171036)supported by the National Natural Science Foundation of China
文摘To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
基金supported by the National High Technology Research & Development Program of China (No.2007AA04Z319)
文摘A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.
