An efficient wear-leveling-aware multi-grained allocator for persistent memory file systems

Persistent memory(PM)file systems have been developed to achieve high performance by exploiting the advanced features of PMs,including nonvolatility,byte addressability,and dynamic random access memory(DRAM)like performance.Unfortunately,these PMs suffer from limited write endurance.Existing space management strategies of PM file systems can induce a severely unbalanced wear problem,which can damage the underlying PMs quickly.In this paper,we propose a Wear-leveling-aware Multi-grained Allocator,called WMAlloc,to achieve the wear leveling of PMs while improving the performance of file systems.WMAlloc adopts multiple min-heaps to manage the unused space of PMs.Each heap represents an allocation granularity.Then,WMAlloc allocates less-worn blocks from the corresponding min-heap for allocation requests.Moreover,to avoid recursive split and inefficient heap locations in WMAlloc,we further propose a bitmap-based multi-heap tree(BMT)to enhance WMAlloc,namely,WMAlloc-BMT.We implement WMAlloc and WMAlloc-BMT in the Linux kernel based on NOVA,a typical PM file system.Experimental results show that,compared with the original NOVA and dynamic wear-aware range management(DWARM),which is the state-of-the-art wear-leveling-aware allocator of PM file systems,WMAlloc can,respectively,achieve 4.11×and 1.81×maximum write number reduction and 1.02×and 1.64×performance with four workloads on average.Furthermore,WMAlloc-BMT outperforms WMAlloc with 1.08×performance and achieves 1.17×maximum write number reduction with four workloads on average.

CSWL:Cross-SSD Wear-Leveling Method in SSD-Based RAID Systems for System Endurance and Performance

Flash memory has limited erasure/program cycles. Hence, to meet their advertised capacity all the time, flash-based solid state drives （SSDs） must prolong their life span through a wear-leveling mechanism. As a very important part of flash translation layer （FTL）, wear leveling is usually implemented in SSD controllers, which is called internal wear leveling. However, there is no wear leveling among SSDs in SSD-based redundant array of independent disks （RAIDs） systems, making some SSDs wear out faster than others. Once an SSD fails, reconstruction must be triggered immediately, but the cost of this process is so high that both system reliability and availability are affected seriously. We therefore propose cross-SSD wear leveling （CSWL） to enhance the endurance of entire SSD-based RAID systems. Under the workload of random access pattern, parity stripes suffer from much more updates because updating to a data stripe will cause the modification of other all related parity stripes. Based on this principle, we introduce an age-driven parity distribution scheme to guarantee wear leveling among flash SSDs and thereby prolong the endurance of RAID systems. Furthermore, age-driven lc,arity distribution benefits performance by maintaining better load balance the life span and performance of SSD-based RAID. With insignificant overhead, CSWL can significantly improve both

TrueFFS文件系统技术研究及实现

TrueFFS技术的出现为丰富的flash存储设备提供了一个统一的块设备接口。论文简要介绍了TrueFFS的工作原理,说明其在flash存储应用中的关键作用,并通过实际案例展示了TrueFFS的硬件实现特点。文中系基于VxWorks操作系统所写,但目前TrueFFS几乎已支持所有的操作系统。

Endurance Awarded Compiling Optimization

The unbanlanced updating frequency of data reduces the endurance of the whole non-volatile main memory that affects the system’s stability significantly. Wear-leveling techniques are effective methods to increase the endurance of non-volatile memory. In this paper, we propose a pure software based low cost wear-leveling method, called writing balance aware mandatory rewriting insertion optimization（WBAMRI）, to improve the dynamic wear-leveling techniques.This method uses the mandatory rewriting operation combined with simple dynamic wear-leveling techniques to switch the code area to hot area dynamically. From the result of simulation, we can see that： 1） Compared with dynamic wear-leveling techniques, our ware-leveling method makes the endurance of non-volatile memory 6 times longer; 2） Compared with static wear-leveling techniques, our method nearly gets the same endurance but without the complex hardware design and the lose of memory access performance.