SOI Waveguides Fabricated by Wet-Etching Method

SOI waveguides fabricated by wet-etching method are demonstrated.The single mode waveguide and 1×2 3dB MMI splitter are analyzed and designed by three dimensional beam propagation method to correct the error of effective index method and guided mode method.The devices are fabricated.Excellent performances,such as low propagation loss of -1.37dB/cm,low excess loss of -2.2dB,and good uniformity of 0.3dB,are achieved.

Heuristic tabu search scheduling algorithm for wet-etching systems in semiconductor wafer fabrications

To improve overall equipment efficiency(OEE) of a semiconductor wafer wet-etching system,a heuristic tabu search scheduling algorithm is proposed for the wet-etching process in the paper,with material handling robot capacity and wafer processing time constraints of the process modules considered.Firstly,scheduling problem domains of the wet-etching system(WES) are assumed and defined,and a non-linear programming model is built to maximize the throughput with no defective wafers.On the basis of the model,a scheduling algorithm based on tabu search is presented in this paper.An improved Nawaz,Enscore,and Ham(NEH) heuristic algorithm is used as the initial feasible solution of the proposed heuristic algorithm.Finally,performances of the proposed algorithm are analyzed and evaluated by simulation experiments.The results indicate that the proposed algorithm is valid and practical to generate satisfied scheduling solutions.

Effect of internal structure of a batch-processing wet-etch reactor on fluid flow and heat transfer

Batch-processing wet-etch reactors are the key equipment widely used in chip fabrication,and their performance is largely affected by the internal structure.This work develops a three-dimensional computational fluid dynamics(CFD)model considering heat generation of wet-etching reactions to investigate the fluid flow and heat transfer in the wet-etch reactor.The backflow is observed below and above the wafer region,as the flow resistance in this region is high.The temperature on the upper part of a wafer is higher due to the accumulation of reaction heat,and the average temperature of the side wafer is highest as its convective heat transfer is weakest.Narrowing the gap between wafer and reactor wall can force the etchant to flow in the wafer region and then facilitate the convective heat transfer,leading to better within-wafer and wafer-to-wafer etch uniformities.An inlet angle of 60°balances fluid by-pass and mechanical energy loss,and it yields the best temperature and etch uniformities.The batch with 25wafers has much wider flow channels and much lower flow resistance compared with that with 50wafers,and thus it shows better temperature and etch uniformities.These results and the CFD model should serve to guide the optimal design of batch-processing wet-etch reactors.

Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAIAs/InGaAs InP-based HEMTs

A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etching-selectivity ratio of InGaAs to InA1As material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide （H202）. Selective wet-etching is validated in the gate-recess process of InA1As/InGaAs InP-based HEMTs, which proceeds and auto- matically stops at the InA1As barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAIAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAIAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic trans- conductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.

Oxidation-based wet-etching method for Al Ga N/Ga N structure with different oxidation times and temperatures

In this article, a detailed analysis of the wet- etching technique for AIGaN/GaN heterostructure using dry thermal oxidation followed by a wet alkali etching was performed. The experimental results show that the oxida- tion plays a key role in the wet-etching method and the etching depth is mainly determined by the oxidation tem- perature and time. The correlation of etching roughness with oxidation time and temperature was investigated. It is found that there exists a critical oxidation temperature in the oxidation process. Finally, a physical explanation of the oxidation procedure for A1GaN layer was given.

Improved optical performance of GaN grown on pattered sapphire substrate

An improved GaN film with low dislocation density was grown on a C-face patterned sapphire substrate （PSS） by metalorganic chemical vapor deposition （MOCVD）. The vapor phase epitaxy starts from the regions with no etched pits and then spreads laterally to form a continuous GaN film. The properties of the GaN film have been investigated by double crystal X-ray diffraction （DCXRD）, atomic force microscopy （AFM） and photoluminescence （PL）, respectively. The full-width at half-maximum （FWHM） of the X-ray diffraction curves （XRCs） for the GaN film grown on PSS in the （0002） plane and the （1012） plane are as low as 312.80 arcsec and 298.08 acrsec, respectively. The root mean square （RMS） of the GaN film grown on PSS is 0.233 nm and the intensity of the PL peak is comparatively strong.