Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration

An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.

6-T CMOS SRAM单元稳定性分析及设计优化

介绍了一种由两个交叉耦合反向器构成的6-晶体管(6-T)存储单元的噪声容限分析方法。对6-T CMOS SRAM单元的稳定性作了分析及仿真。借助SPICE和MATLAB工具,对存储单元在数据保持和数据读取时的稳定性、数据写入过程中的可靠性及其之间的关系进行了深入研究。对可能影响噪声容限的因素,如单元比、上拉比、MOS管的阈值电压、位线预充电压、电源电压以及温度进行了仿真讨论,并从中得到合适的电路设计参数。流片结果表明,理论分析与实测数据相符。分析数据对基于CSMC 0.5μm CMOS工艺的SRAM电路设计优化具有指导作用。

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

The use of Internet of Things(IoT)applications become dominant in many systems.Its on-chip data processing and computations are also increasing consistently.The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications.The cache memory designed on Static Random-Access Memory(SRAM)cell with features such as low power,high speed,and process tolerance are highly important for the IoT memory system.Therefore,a process tolerant SRAM cell with low power,improved delay and better stability is presented in this research paper.The proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55%and 47.75%for write and 35.59%and 36.56%for read operations compared to 6 T and 8 T SRAM cells.The cell shows an improved write delay of 26.46%and 37.16%over 6 T and 8T and read delay is lowered by 50.64%and 72.90%against 6 T and 10 T cells.The symmetric design used in core latch to improve the write noise margin(WNM)by 17.78%and 6.67%whereas the single ended separate read circuit improves the Read Static Noise Margin(RSNM)by 1.88x and 0.33x compared to 6 T and 8T cells.The read power delay product and write power delay product are lower by 1.94x,1.39x and 0.17x,2.02x than 6 T and 8 T cells respectively.The lower variability from 5000 samples validates the robustness of the proposed cell.The simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit(GPDK)45 nm technology file in this work.

Effect of Temperature &Supply Voltage Variation on Stability of 9T SRAM Cell at 45 nm Technology for Various Process Corners

Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.