New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In fir...In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 - 0.964] GHz with [279.429 - 16.515] μW power consumption variation. VCO designed with five XNOR delay cells shows frequency variation of [1.152 - 0.575] GHz with varying power consumption of [465.715 - 27.526] μW. In the second method VCO having three XOR stages shows frequency variation [1.9176 - 1.029] GHz with power consumption variation from [296.393 - 19.051] μW. A five stage XOR based VCO design shows frequency variation [1.049 - 0.565] GHz with power consumption variation from [493.989 - 31.753] μW. Simulations have been performed by using SPICE based on TSMC 0.18μm CMOS technology. Power consumption and output frequency range of proposed VCOs have been compared with earlier reported circuits and proposed circuit’s shows improved performance.展开更多
By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked tran...By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic （DTCTGAL） circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.展开更多
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
文摘In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 - 0.964] GHz with [279.429 - 16.515] μW power consumption variation. VCO designed with five XNOR delay cells shows frequency variation of [1.152 - 0.575] GHz with varying power consumption of [465.715 - 27.526] μW. In the second method VCO having three XOR stages shows frequency variation [1.9176 - 1.029] GHz with power consumption variation from [296.393 - 19.051] μW. A five stage XOR based VCO design shows frequency variation [1.049 - 0.565] GHz with power consumption variation from [493.989 - 31.753] μW. Simulations have been performed by using SPICE based on TSMC 0.18μm CMOS technology. Power consumption and output frequency range of proposed VCOs have been compared with earlier reported circuits and proposed circuit’s shows improved performance.
基金Project supported by the National Natural Science Foundation of China (No.60776022)the Science and Technology Fund of Zhejiang Province (No.2008C21166)+1 种基金the New Shoot Talents Program of Zhejiang Province (No.2008R40G2070015)the Natural Science Foundation of Ningbo (No.2009A610059)
文摘By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic （DTCTGAL） circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.
