Review of flexible and transparent thin-film transistors based on zinc oxide and related materials

Flexible and transparent electronics enters into a new era of electronic technologies.Ubiquitous applications involve wearable electronics,biosensors,flexible transparent displays,radio-frequency identifications（RFIDs）,etc.Zinc oxide（ZnO） and relevant materials are the most commonly used inorganic semiconductors in flexible and transparent devices,owing to their high electrical performances,together with low processing temperatures and good optical transparencies.In this paper,we review recent advances in flexible and transparent thin-film transistors（TFTs） based on ZnO and relevant materials.After a brief introduction,the main progress of the preparation of each component（substrate,electrodes,channel and dielectrics） is summarized and discussed.Then,the effect of mechanical bending on electrical performance is highlighted.Finally,we suggest the challenges and opportunities in future investigations.

Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.

Contact resistance asymmetry of amorphous indium–gallium–zinc–oxide thin-film transistors by scanning Kelvin probe microscopy

In this work, a method based on scanning Kelvin probe microscopy is proposed to separately extract source/drain（S/D） series resistance in operating amorphous indium–gallium–zinc–oxide（a-IGZO） thin-film transistors. The asymmetry behavior of S/D contact resistance is deduced and the underlying physics is discussed. The present results suggest that the asymmetry of S/D contact resistance is caused by the difference in bias conditions of the Schottky-like junction at the contact interface induced by the parasitic reaction between contact metal and a-IGZO. The overall contact resistance should be determined by both the bulk channel resistance of the contact region and the interface properties of the metalsemiconductor junction.

Effects of annealing process on characteristics of fully transparent zinc tin oxide thin-film transistor

Annealing effect on the performance of fully transparent thin-film transistor （TTFT）, in which zinc tin oxide （ZnSnO） is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/（V.s） and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

Si-doped zinc oxide（SZO） thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated.Moreover,the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure.The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm,and the optical band gap of the SZO film gradually increases with increasing Si content.The Si-doping can effectively suppress the grain growth of ZnO,revealed by atomic force microscope analysis.Compared with that of the undoped ZnO TFT,the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10^-12 A,and thus the on/off current ratio is increased by more than two orders of magnitude.In summary,the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 10^6 and superior stability under gate-bias and drain-bias stress.

High-throughput fabrication and semi-automated characterization of oxide thin film transistors

High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect the material properties under varying measurement conditions.Similarly,multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance.In this work,we apply these high throughput experimental methods to thin film transistors(TFTs),demonstrating combinatorial channel layer growth,device fabrication,and semi-automated characterization using sputtered oxide TFTs as a case study.We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library,such as channel thickness and length,channel cation compositions,and oxygen atmosphere during deposition.We also present a semi-automated method to measure the 44 devices fabricated on a 50 mm×50 mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time.Finally,we propose a fully automated characterization system for similar TFT libraries,which can be coupled with high throughput data analysis.These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.

Fabrication of Bottom-Gate and Top-Gate Transparent ZnO Thin Film Transistors

Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films served as the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performance than those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode, which have clear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off ratio were determined to be 18.4cm^2/（V ·s）, - 0. 5V and 10^4 , respectively. Meanwhile, the top-gate ZnO-TFTs exhibit n-chan- nel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices may be due to the different character of the interface between the channel and insulator layers. The two transistors types have high transparency in the visible light region.

Degradation of current–voltage and low frequency noise characteristics under negative bias illumination stress in InZnO thin film transistors

The instabilities of indium–zinc oxide thin film transistors under bias and/or illumination stress are studied in this paper. Firstly, illumination experiments are performed, which indicates the variations of current–voltage characteristics and electrical parameters（such as threshold voltage and sub-threshold swing） are dominated by the stress-induced ionized oxygen vacancies and acceptor-like states. The dependence of degradation on light wavelength is also investigated. More negative shift of threshold voltage and greater sub-threshold swing are observed with the decrease of light wavelength.Subsequently, a negative bias illumination stress experiment is carried out. The degradation of the device is aggravated due to the decrease of recombination effects between ionized oxygen vacancies and free carriers. Moreover, the contributions of ionized oxygen vacancies and acceptor-like states are separated by using the mid-gap method. In addition, ionized oxygen vacancies are partially recombined at room temperature and fully recombined at high temperature. Finally, low-frequency noise is measured before and after negative bias illumination stress. Experimental results show few variations of the oxide trapped charges are generated during stress, which is consistent with the proposed mechanism.

Threshold voltage tuning and printed complementary transistors and inverters based on thin films of carbon nanotubes and indium zinc oxide

Carbon nanotubes （CNTs） have emerged as an important material for printed macroelectronics. However, achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging to make reliable n-type CNT transistors. In this study, we report threshold voltage （Vth） tuning and printing of complementary transistors and inverters composed of thin films of CNTs and indium zinc oxide （IZO） as p-type and n-type transistors, respectively. We have optimized the Vth of p-type transistors by comparing Ti/Au and Ti/Pd as source/drain electrodes, and observed that CNT transistors with Ti/Au electrodes exhibited enhancement mode operation （Vth 〈 0）. In addition, the optimized In：Zn ratio offers good n-type transistors with high on-state current （Ion） and enhancement mode operation （Vth 〉 0）. For example, an In：Zn ratio of 2：1 yielded an enhancement mode n-type transistor with Vth - 1 V and Ion of 5.2 μA. Furthermore, by printing a CNT thin film and an IZO thin film on the same substrate, we have fabricated a complementary inverter with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work shows the promise of the hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits.

Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.

有源层溅射工艺及后退火温度对IZO TFT电性能的影响

为了提高氧化物薄膜晶体管的器件性能,以掺In氧化锌(IZO)为有源层,原子层沉积法(ALD)沉积的Al2O3薄膜为栅介层,制备了基于IZO的薄膜晶体管(IZO TFT),研究了IZO薄膜制备工艺中溅射气体氩氧流量比、溅射压强和后退火温度等工艺参数对TFT器件电学性能的影响。结果表明,在恰当的氩氧比和反应气压以及相对较高的退火温度下制备的IZO TFT具有良好的电学特性,当氩氧流量比为60:20 sccm、溅射压强为0.5 Pa、空气气氛中以250℃退火1 h时后,IZO TFT器件的整体电学特性表现较优,其迁移率高达31 cm^(2)/(V·s),开关电流比大于108。相对过低或过高的氩氧比会导致IZO有源层中氧空位含量过低或过高,从而降低TFT器件性能。过低的退火温度不足以使栅介质的Al-OH转变成Al-O以及空气中的氧扩散进入IZO体内钝化氧空位,因此器件性能较差。

IGZO薄膜晶体管生物传感器无标记检测强直性脊柱炎

为了快速检测强直性脊柱炎血清学分子标志物人体白细胞抗原(HLA-B27),开发了一种基于人体白细胞抗原B27(HLA-B27)功能化的氧化铟镓锌(IGZO)薄膜晶体管生物传感器。利用射频磁控溅射技术和微纳加工工艺制备了IGZO薄膜晶体管(IGZO TFT),采用3-氨丙基三乙氧基硅烷(APTES)和抗体对IGZO TFT进行修饰,制备出针对HLA-B27检测的生物传感器。实验结果表明,功能化的IGZO TFT生物传感器具有稳定的电学特性和传感性能。传感器对HLA-B27的检测极限为1 pg/mL,在1 pg/mL至100 ng/mL的范围内均有良好的线性响应。这说明所设计的高性能生物传感器能够有效检测出强直性脊柱炎的标志物。此外,IGZO TFT可以扩展为传感器阵列平台,实现对某种疾病多种标志物的联合检测,在便携式床旁诊断设备的应用中具有巨大潜力。

IAZO薄膜晶体管的制备与性能研究

为了探究退火温度对IAZO薄膜晶体管器件光电性能的影响,采用射频溅射单溅射法,并在(400~700)℃的范围内制备了一系列真空退火后的IAZO薄膜晶体管。分别对IAZO薄膜表面形貌、内部结构、元素组成和价态组成进行分析,采用半导体参数仪及搭配的探针台测试电学性能测试。采用紫外可见分光光度计测试薄膜透过率。结果表明,随着退火温度的升高,器件的电学性能先呈现上升趋势,达到峰值后开始下降。在500 ℃真空退火1 h后,IAZO TFT饱和迁移率为0.18 cm2/(V·s)、阈值电压为3.35 V、亚阈值摆幅为0.10 V/decade、开关比为1.13*108。IAZO薄膜透光率达到90 %以上、光学带隙达到4.1 eV,器件性能达到最佳。

顶栅共面结构非晶氧化物薄膜晶体管的低成本制备及性能研究

将溶液法制备的不含镓的非晶InAlZnO薄膜和有机聚甲基丙烯酸甲酯薄膜分别作为沟道层和介质层,制备了顶栅共面结构的非晶氧化物薄膜晶体管(TFT)器件,探讨了沟道层中Al含量对器件性能的影响。结果表明:Al对InZnO薄膜中氧空位的形成能起到一定抑制作用,增加Al含量即可降低沟道层中的电子载流子浓度,使得InAlZnO TFT器件阈值电压正向移动、关态电流减小,以有利于器件开关比的提升。此外,基于沟道层中Al含量的调整可通过优化沟道层/介质层界面状态来促进器件阈值电压滞回稳定性的提升。当沟道层中Al含量为30%时,制备的器件具有最佳综合性能。

高浓度掺杂非晶铟镓锌氧化物薄膜的态密度模型研究

针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟研究态密度关键参数对器件性能的影响,以此揭示a-IGZO TFTs中制备工艺对导电沟道修复的物理机理.首先,采用结合强度较高的钼/铜双层结构作为栅/源/漏电极,引入BCE方法制备了底栅顶接触(BottomGate Top-Contact,BG-TC)TFTs.其次,建立了适用于BCE技术的a-IGZO TFTs的HCD-DOS模型.随后,基于TCAD(Technology Computer Aided Design)仿真器对态密度关键参数进行数值研究,结果表明,不同态密度参数对a-IGZO TFTs器件转移特性曲线、电学特性以及沟道内部电子浓度分布的影响有所差异.最后,基于HCD-DOS模型探索SiO_(x)钝化层沉积和N_(2)O等离子体处理对器件内部机理的影响.研究发现,N2O等离子体处理对态密度分布和沟道载流子浓度有显著影响,进而导致阈值电压正向漂移.

纳米氧化锌粒子薄膜的场效应载流子迁移率特性的研究

将纳米氧化锌粒子制备纳米膜,研究其场效应性能与载流子迁移性能。通过在有机溶剂介质中热分解油酸锌配合物,合成出尺寸均匀的六方相氧化锌纳米晶粒子。以沉积了铝钛氧化物层与铟锡氧化物层的玻璃为载体,通过旋涂工艺将纳米氧化锌粒子涂覆于其表面,制备出场效应薄膜晶体管。通过工艺优化,制成的半导体纳米氧化锌薄膜晶体管具有优异的可控结构及致密分布的氧化锌纳米晶体,表现出优异的场效应性能与载流子迁移性能。这种直接由氧化锌纳米晶制备的薄膜晶体管具有非毒性、好的透明性以及优越而稳定的场效应半导体器件性能。该技术可高效,便利且低成本大批量地制备氧化锌薄膜晶体管,便于后续在电子等领域的应用。

高性能ZnSnO∶Li/ZnSnO双有源层TFT电学性能的研究

双有源层以迁移率高、开关比高、大面积均匀性好等优点成为近年研究热点。采用射频磁控溅射方法,制备了ZnSnO∶Li/ZnSnO薄膜晶体管(TFT),对其电学特性进行了测试,并研究了器件迁移率提高的原因及其内在的微观机制。研究发现,ZTO∶Li/ZTO TFT表现出了良好的电学特性,其场效应迁移为率为13.98 cm^(2)/(V·s),亚阈值摆幅为0.84 V/dec,开关比为1.13×10^(9)。通过XPS对其薄膜进行分析发现,Li的引入导致薄膜中氧和金属结合键的浓度增加,氧空位浓度减少,从而使得TFT的迁移率增大,开关比增大,亚阈值摆幅减小。