All-silicon carrier accumulation modulator based on a lateral metal-oxide-semiconductor capacitor

In silicon photonics, the carrier depletion scheme has been the most commonly used mechanism for demonstrating high-speed electro-optic modulation. However, in terms of phase modulation efficiency, carrieraccumulation-based devices potentially offer almost an order of magnitude improvement over those based on carrier depletion. Previously reported accumulation modulator designs only considered vertical metal-oxidesemiconductor(MOS) capacitors, which imposes serious restrictions on the design flexibility and integratability with other photonic components. In this work, for the first time to our knowledge, we report experimental demonstration of an all-silicon accumulation phase modulator based on a lateral MOS capacitor. Using a Mach–Zehnder interferometer modulator with a 500-μm-long phase shifter, we demonstrate high-speed modulation up to 25 Gbit∕s with a modulation efficiency(V_πL_π) of 1.53 V·cm.

Interfacial and electrical properties of HfAIO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation

Interfacial and electrical properties of HfA10/GaSb metal-oxide-semiconductor capacitors （MOSCAPs） with sulfur passivation were investigated and the chemical mechanisms of the sulfur passivation process were carefully studied. It was shown that the sulfur passivation treatment could reduce the interface trap density Dit of the HfAIO/GaSb interface by 35% and reduce the equivalent oxide thickness （EOT） from 8 nm to 4 nm. The improved properties are due to the removal of the native oxide layer, as was proven by x-ray photoelectron spectroscopy measurements and high-resolution cross-sectional transmission electron microscopy （HRXTEM） results. It was also found that GaSb-based MOSCAPs with HfA10 gate dielectrics have interfacial properties superior to those using HfO2 or A1203 dielectric layers.

Interfacial and Electrical Properties of GaAs Metal-Oxide-Semiconductor Capacitor with ZrAlON as the Interfacial Passivation Layer

The ZrTiON gate-dielectric GaAs metal-oxide-semiconductor （MOS） capacitors with or without ZrAION as the interfacial passivation layer （IPL） are fabricated and their properties are investigated. The experimental results show that the GaAs MOS capacitor with the ZrAION IPL exhibits better interracial and electrical properties, including lower interface-state density （1.14 × 10^12 cm^-2eV^-1）, smaller gate leakage current （6.82 × 10^-5 A//cm^2 at Vfb ＋1V）, smaller capacitance equivalent thickness （1.5 nm）, and larger k value （26）. The involved mechanisms lie in the fact that the ZrAION IPL can effectively block the diffusion of Ti and O towards the GaAs surface, thus suppressing the formation of interracial Ga-/As-oxides and As-As dimers, which leads to improved interracial and electrical properties for the devices.

Comparative study of electrical characteristics for n-type 4H–SiC planar and trench MOS capacitors annealed in ambient NO

The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal-oxide-semiconductor （MOS） capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250 ℃ in NO ambient for above 1 h due to the increasing interface shallow and fast states. These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the （1120） and （1100） faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the （0001） face under the same NO annealing condition. In addition, it is found that Fowler-Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device. However, Poole-Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO2/SiC interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO2/SiC interfaces.

Electrical characteristics of MOS capacitor with HfTiON gate dielectric and HfTiSiON interlayer

The paper reports that Hfrio dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambience, followed by an annealing in different gas ambiences of N2, NO and NH3 at 600℃ for 2 min. Capacitancevoltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si≡N bonds to passivate dangling Si bonds and replace strained Si-O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.

Low voltage program-erasable Pd-Al_2O_3-Si capacitors with Ru nanocrystals for nonvolatile memory application

Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application. While keeping the entire insulator Al2O3 thickness fixed, the memory window has a strong dependence on the tunneling layer thickness under low operating voltages, whereas it has weak dependence under high operating voltages. As for the optimal configuration comprised of 6-nm tunneling layer and 22-nm blocking layer, the resulting memory window increases from 1.5 V to 5.3 V with bias pulse increasing from 10-5 s to 10-2 s under ±7 V. A ten-year memory window as large as 5.2 V is extrapolated at room temperature after ±8 V/1 ms programming/erasing pulses.

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.

Temperature dependent interfacial and electrical characteristics during atomic layer deposition and annealing of HfO_2 films in p-GaAs metal–oxide–semiconductor capacitors

We have investigated the temperature dependent interfacial and electrical characteristics of p-GaAs metal-oxide-semiconductor capacitors during atomic layer deposition （ALD） and annealing of HfO2 using the tetrakis （ethylmethyl） amino hafnium precursor. The leakage current decreases with the increase of the ALD tem- perature and the lowest current is obtained at 300 ℃ as a result of the Frenkel-Poole conduction induced leakage current being greatly weakened by the reduction of interfacial oxides at the higher temperature. Post deposition annealing （PDA） at 500 ℃ after ALD at 300 ℃ leads to the lowest leakage current compared with other annealing temperatures. A pronounced reduction in As oxides during PDA at 500 ℃ has been observed using X-ray pho- toelectron spectroscopy at the interface resulting in a proportional increase in Ga203. The increment of Ga203 after PDA depends on the amount of residual As oxides after ALD. Thus, the ALD temperature plays an important role in determining the high-k/GaAs interface condition. Meanwhile, an optimum PDA temperature is essential for obtaining good dielectric properties.

Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

The trigger voltage walkin effect has been investigated by designing two different laterally diffused metal-oxide-semiconductor （LDMOS） transistors with an embedded silicon controlled rectifier （SCR）. By inserting a P＋ implant region along the outer and the inner boundary of the N＋ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5/zm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse （TLP） and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

The physical mechanisms triggering electrostatic discharge （ESD） in high voltage LDMOS power transistors （〉 160 V） under transmission line pulsing （TLP） and very fast transmission line pulsing （VFTLP） stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.