An Adaptive Ramp Generator for ADC Built-in Self-Test

An adaptive ramp generator based on linear histogram was proposed for the built-in selftest (BIST) of analog to digital convertor (ADC) in CMOS image sensor. By comparing the generated ramp signal to a reference voltage and feeding back a calibration signal, the slope adjustment was implemented, and high linearity and precision of ramp slope were realized. By modulating the pulse width and reference voltage, sweep length varied from microsecond to second and signal swing could reach 3 V with 5.6 mW power consumption. The ramp was used as input to an ideal 10-bit single-slope ADC, and the corresponding DNL and INL were 0.032 LSB and 0.078 LSB, re-spectively.

Dynamic analysis and fractional-order adaptive sliding mode control for a novel fractional-order ferroresonance system

Ferroresonance is a complex nonlinear electrotechnical phenomenon, which can result in thermal and electrical stresses on the electric power system equipments due to the over voltages and over currents it generates. The prediction or determination of ferroresonance depends mainly on the accuracy of the model used. Fractional-order models are more accurate than the integer-order models. In this paper, a fractional-order ferroresonance model is proposed. The influence of the order on the dynamic behaviors of this fractional-order system under different parameters n and F is investigated. Compared with the integral-order ferroresonance system, small change of the order not only affects the dynamic behavior of the system, but also significantly affects the harmonic components of the system. Then the fractional-order ferroresonance system is implemented by nonlinear circuit emulator. Finally, a fractional-order adaptive sliding mode control （FASMC） method is used to eliminate the abnormal operation state of power system. Since the introduction of the fractional-order sliding mode surface and the adaptive factor, the robustness and disturbance rejection of the controlled system are en- hanced. Numerical simulation results demonstrate that the proposed FASMC controller works well for suppression of ferroresonance over voltage.

A highly linear power amplifier for WLAN

A three-stage power amplifier （PA） for WLAN application in 2.4-2.5 GHz is presented. The proposed PA employs an adaptive bias circuit to adjust the operating point of the PA to improve the linearity of the PA. Two methods to short the 2nd harmonic circuit are compared in the area of efficiency and gain of the PA. The PA is taped out in the process of 2/zm InGaP/GaAs HBT and is tested by the evaluation board. The measured results show that 31.5 dB power gain and 29.3 dBm PldB with an associated 40.4% power added efficiency （PAE） under the single tone stimulus. Up to 26.5 dBm output power can be achieved with an error vector magnitude （EVM） of lower than 3% under the 64QAM/OFDM WLAN stimulus.