In a system based on the phase lock loop(PLL), a trade-off must be made between the tracking precision and the dynamic performance if constant parameters are adopted. To overcome this drawback, a new method called no ...In a system based on the phase lock loop(PLL), a trade-off must be made between the tracking precision and the dynamic performance if constant parameters are adopted. To overcome this drawback, a new method called no phase slipping adaptive bandwidth(NPS-AB) is proposed, which can adjust the loop bandwidth adaptively for different working conditions. As a result, both the tracking precision and the dynamic performance can be achieved concurrently. NPS-AB has two features to keep the loop stable: one is the capability of quick response to dynamics; the other is a series of additional constraints when the bandwidth is switched. Compared with other methods, there is no phase slipping during the adjustment process for NPS-AB. The phase integer ambiguity can be avoided and the phase value is kept valid. It is meaningful for carrier ranging systems. Simulation results show that NPS-AB can deal with sudden dynamics and keep the pseudo-range value stable in the entire dynamic process.展开更多
Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying freq...Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).展开更多
High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase...High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.展开更多
Winding and web transport systems are subjected to quasi-periodic disturbances of the web tension due to the eccentricity and the non-circularity of the reel and rolls. The disturbances induced by the non-circularity ...Winding and web transport systems are subjected to quasi-periodic disturbances of the web tension due to the eccentricity and the non-circularity of the reel and rolls. The disturbances induced by the non-circularity and eccentricity of the rolls are quasi-periodic with a frequency that varies with their rotation speed. An adaptive method of rejection of these disturbances is proposed in this paper. It is based on a phase-locked loop structure that estimates simutaneously the phase and magnitude of the perturbation and then cancels it. This algorithm can be plugged in an existing industrial controller. The stability and robustness of the algorithm are also discussed. The ability of the algorithm to reject quasi-periodic disturbances with slowly varying frequencies is shown through simulation results.展开更多
The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock ...The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.展开更多
文摘In a system based on the phase lock loop(PLL), a trade-off must be made between the tracking precision and the dynamic performance if constant parameters are adopted. To overcome this drawback, a new method called no phase slipping adaptive bandwidth(NPS-AB) is proposed, which can adjust the loop bandwidth adaptively for different working conditions. As a result, both the tracking precision and the dynamic performance can be achieved concurrently. NPS-AB has two features to keep the loop stable: one is the capability of quick response to dynamics; the other is a series of additional constraints when the bandwidth is switched. Compared with other methods, there is no phase slipping during the adjustment process for NPS-AB. The phase integer ambiguity can be avoided and the phase value is kept valid. It is meaningful for carrier ranging systems. Simulation results show that NPS-AB can deal with sudden dynamics and keep the pseudo-range value stable in the entire dynamic process.
文摘Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).
基金This work was supported in part by Lodam A/S and in part by the PSO-ELFORSK Program。
文摘High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.
文摘Winding and web transport systems are subjected to quasi-periodic disturbances of the web tension due to the eccentricity and the non-circularity of the reel and rolls. The disturbances induced by the non-circularity and eccentricity of the rolls are quasi-periodic with a frequency that varies with their rotation speed. An adaptive method of rejection of these disturbances is proposed in this paper. It is based on a phase-locked loop structure that estimates simutaneously the phase and magnitude of the perturbation and then cancels it. This algorithm can be plugged in an existing industrial controller. The stability and robustness of the algorithm are also discussed. The ability of the algorithm to reject quasi-periodic disturbances with slowly varying frequencies is shown through simulation results.
文摘The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.
