This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector...This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.展开更多
基金Project supported by the National Nature Science Foundation of China(Nos.61331003,61474108)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China(No.2016ZX03001002)
文摘This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.
