针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control l...This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.展开更多
针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电...针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电路中各种非理想噪声的表达式进行精确推导,根据系统中的运放功耗指标进行参数优化;最后分别在MATLAB和Cadence软件中建立模型,进行100点蒙特卡洛仿真。仿真结果表明,在TSMC 180 nm工艺失配下,该流水线ADC有效位数达到9.70 bit,无杂散动态范围维持在76 dB附近,微分非线性在0.3 LSB以内,积分非线性在0.5 LSB以内,核心功耗在8 mW,该分析方法在保证流水线ADC优异性能的同时,大幅提高了设计效率。展开更多
逐次逼近寄存器模数转换器(SAR ADC)在逐次逼近的过程中,电容的切换会使参考电压上出现参考纹波噪声,该噪声会影响比较器的判定,进而输出错误的比较结果。针对该问题,基于CMOS 0.5μm工艺,设计了一种具有纹波消除技术的10 bit SAR ADC...逐次逼近寄存器模数转换器(SAR ADC)在逐次逼近的过程中,电容的切换会使参考电压上出现参考纹波噪声,该噪声会影响比较器的判定,进而输出错误的比较结果。针对该问题,基于CMOS 0.5μm工艺,设计了一种具有纹波消除技术的10 bit SAR ADC。通过增加纹波至比较器输入端的额外路径,将参考纹波满摆幅输入至比较器中;同时设计了消除数模转换器(DAC)模块,对参考纹波进行采样和输入,通过反转纹波噪声的极性,消除参考纹波对ADC输出的影响。该设计将信噪比(SNR)提高到56.75 dB,将有效位数(ENOB)提升到9.14 bit,将积分非线性(INL)从-1~5 LSB降低到-0.2~0.3 LSB,将微分非线性(DNL)从-3~4 LSB降低到-0.5~0.5 LSB。展开更多
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
基金supported by Qingdao Hi-image Technologies Co., Ltdin part by the NSFC of China under Grant 62174149, 61974118, 62004156the National Key R&D Program of China under Grant 2022YFC2404902
文摘This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.
文摘针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电路中各种非理想噪声的表达式进行精确推导,根据系统中的运放功耗指标进行参数优化;最后分别在MATLAB和Cadence软件中建立模型,进行100点蒙特卡洛仿真。仿真结果表明,在TSMC 180 nm工艺失配下,该流水线ADC有效位数达到9.70 bit,无杂散动态范围维持在76 dB附近,微分非线性在0.3 LSB以内,积分非线性在0.5 LSB以内,核心功耗在8 mW,该分析方法在保证流水线ADC优异性能的同时,大幅提高了设计效率。
