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IMPROVED ALGORITHM FOR STRIPMAP SAR IMAGING
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作者 Wei Qing Yang Shaoquan Luo Ming Dong Chunxi 《Journal of Electronics(China)》 2006年第2期216-219,共4页
This paper proposes a calibrated method for quasi-broadside side-looking mode SAR imaging with small squint angle and an improved method named as phase alignment algorithm of subaperture reference signal. The calibrat... This paper proposes a calibrated method for quasi-broadside side-looking mode SAR imaging with small squint angle and an improved method named as phase alignment algorithm of subaperture reference signal. The calibrated method adopts subaperture spotlighting algorithm of broadside mode to image the real data of quasi-broadside mode SAR, then based on the obtained image the small squint angle is estimated and the calibrated subaperture spotlighting algorithm of squint mode is employed to obtain the final image. The calibrated method can calibrate the abnormal region and obtain the correct image. The phase alignment algorithm of subaperture reference signal adjusts phases of respective subaperture reference signals in order to make them be in phase and constructs a new spotlighting window function for SAR imaging. Theoretical analysis shows that with the same sample data, the improved method can increase SAR imaging area in azimuth dimension. The methods are verified by the results of computer simulation. 展开更多
关键词 Synthetic Aperture Radar (SAR) Calibrated Squint Subaperture spotlighting phase alignment Reference signal
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5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction
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作者 张长春 王志功 +2 位作者 施思 苗澎 田玲 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第9期96-101,共6页
A 5-Gb/s 2 : 1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS tech... A 5-Gb/s 2 : 1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm^2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system. 展开更多
关键词 MULTIPLEXER clock extraction automatic phase alignment phase frequency detector voltage-controlled oscillator
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