Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber re...<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>展开更多
This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL)....This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex-perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications.展开更多
A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods...A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is investigated. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn(TBT) position resolution better than 1 μm is achieved, and the slow-acquisition(SA) position resolution is improved from 4.28 μm to 0.17 μm.展开更多
智慧园区各类新兴业务在电力物联网(power internet of things,PIo T)设备提供的数据支持下开展。这些业务具有严格的时间同步要求。如何在现有电力线载波通信(power line carrier,PLC)的基础上实现高精度、高可靠时间同步成为关键问题...智慧园区各类新兴业务在电力物联网(power internet of things,PIo T)设备提供的数据支持下开展。这些业务具有严格的时间同步要求。如何在现有电力线载波通信(power line carrier,PLC)的基础上实现高精度、高可靠时间同步成为关键问题。针对上述问题,首先,该文建立基于PLC的智慧园区电力物联网精准时间同步网络模型,根据改进精准时间协议(precision time protocol,PTP)计算同步误差,在此基础上,建立基于数字锁相环的频率偏移补偿模型,降低累积误差;其次,提出站点(station,STA)时间同步误差最小化问题;最后,提出基于经验匹配的电力物联网精准时间同步算法,通过调整时间同步匹配成本,优化STA的时间同步路径选择策略。仿真结果表明,所提方法能有效提高时间同步精度。展开更多
This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） dire...This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） direct sequence spread spectrum （DS-SS） signals with residual carrier. This approach needs some given parameters, such as the period and code rate of PN sequence. The received signal is firstly sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. An autocorrelation matrix is then computed and accumulated by those signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of the autocorrelation matrix. Further more, a digital phase lock loop is used to process the estimated PN sequence, it estimates and tracks the residual carrier and removes the residual carrier in the end. Theory analysis and computer simulation results show that this approach can effectively realize the PN sequence blind estimation from the input DS-SS signals with residual carrier in lower SNR.展开更多
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
文摘<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>
文摘This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex-perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications.
基金Supported by the Knowledge Innovation Program of the Chinese Academy of Sciences(No.KJCX2-YW-N27)National Natural Science Foundation of China(Nos.11205153 and 11175176)
文摘A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is investigated. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn(TBT) position resolution better than 1 μm is achieved, and the slow-acquisition(SA) position resolution is improved from 4.28 μm to 0.17 μm.
文摘智慧园区各类新兴业务在电力物联网(power internet of things,PIo T)设备提供的数据支持下开展。这些业务具有严格的时间同步要求。如何在现有电力线载波通信(power line carrier,PLC)的基础上实现高精度、高可靠时间同步成为关键问题。针对上述问题,首先,该文建立基于PLC的智慧园区电力物联网精准时间同步网络模型,根据改进精准时间协议(precision time protocol,PTP)计算同步误差,在此基础上,建立基于数字锁相环的频率偏移补偿模型,降低累积误差;其次,提出站点(station,STA)时间同步误差最小化问题;最后,提出基于经验匹配的电力物联网精准时间同步算法,通过调整时间同步匹配成本,优化STA的时间同步路径选择策略。仿真结果表明,所提方法能有效提高时间同步精度。
基金supported by the National Natural Science Foundation of China (10776040 60602057)+4 种基金Program for New Century Excellent Talents in University (NCET)the Project of Key Laboratory of Signal and Information Processing of Chongqing (CSTC2009CA2003)the Natural Science Foundation of Chongqing Science and Technology Commission (CSTC2009BB2287)the Natural Science Foundation of Chongqing Municipal Education Commission (KJ060509 KJ080517)
文摘This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） direct sequence spread spectrum （DS-SS） signals with residual carrier. This approach needs some given parameters, such as the period and code rate of PN sequence. The received signal is firstly sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. An autocorrelation matrix is then computed and accumulated by those signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of the autocorrelation matrix. Further more, a digital phase lock loop is used to process the estimated PN sequence, it estimates and tracks the residual carrier and removes the residual carrier in the end. Theory analysis and computer simulation results show that this approach can effectively realize the PN sequence blind estimation from the input DS-SS signals with residual carrier in lower SNR.
