Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance...A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance of super-exponential iteration DFE algorithm.Based on the MSEI-DFE algorithm,it is first proposed to develop an error function as an improvement to the error function of MSEI,which effectively achieves faster convergence speed of the algorithm.Subsequently,a hyperbolic tangent function variable step-size algorithm is developed considering the high variation rate of the hyperbolic tangent function around zero,so as to further improve the convergence speed of the algorithm.In the end,a second-order digital phase-locked loop is introduced into the decision feedback equalizer to track and compensate for the phase rotation of equalizer input signals.For the multipath underwater acoustic channel with mixed phase and phase rotation,quadrature phase shift keying(QPSK)and 16 quadrature amplitude modulation(16QAM)modulated signals are used in the computer simulation of the algorithm in terms of convergence and carrier recovery performance.The results show that the proposed algorithm can considerably improve convergence speed and steady-state error,make effective compensation for phase rotation,and efficiently facilitate carrier recovery.展开更多
本文在介绍了经典全数字锁相环(all digital PLL,AD-PLL)的基础上,提出了具有捕获锁定未知输入信号频率功能的ADPLL,使用方便,应用广泛。本文详尽的描述了系统的工作原理和关键部件的设计,通过计算机进行了仿真验证,并在可编程逻辑器件(...本文在介绍了经典全数字锁相环(all digital PLL,AD-PLL)的基础上,提出了具有捕获锁定未知输入信号频率功能的ADPLL,使用方便,应用广泛。本文详尽的描述了系统的工作原理和关键部件的设计,通过计算机进行了仿真验证,并在可编程逻辑器件(FPGA)中予以实现。展开更多
A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works...A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.展开更多
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
基金supported by the National Natural Science Foundation of China(61671461)。
文摘A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance of super-exponential iteration DFE algorithm.Based on the MSEI-DFE algorithm,it is first proposed to develop an error function as an improvement to the error function of MSEI,which effectively achieves faster convergence speed of the algorithm.Subsequently,a hyperbolic tangent function variable step-size algorithm is developed considering the high variation rate of the hyperbolic tangent function around zero,so as to further improve the convergence speed of the algorithm.In the end,a second-order digital phase-locked loop is introduced into the decision feedback equalizer to track and compensate for the phase rotation of equalizer input signals.For the multipath underwater acoustic channel with mixed phase and phase rotation,quadrature phase shift keying(QPSK)and 16 quadrature amplitude modulation(16QAM)modulated signals are used in the computer simulation of the algorithm in terms of convergence and carrier recovery performance.The results show that the proposed algorithm can considerably improve convergence speed and steady-state error,make effective compensation for phase rotation,and efficiently facilitate carrier recovery.
文摘A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
