THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

Robust CMOS phase frequency detector for high speed and low jitter charge pump PLL

In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.

Design of 0.5V low-voltage phase and frequency detector for frequency synthesizer in wireless sensor networks

Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.

An all-optical phase detector by amplitude modulation of the local field in a Rydberg atom-based mixer

Recently,a Rydberg atom-based mixer was developed to measure the phase of a radio frequency(RF)field.The phase of the signal RF(SIG RF)field is down-converted directly to the phase of a beat signal created by the presence of a local RF(LO RF)field.In this study,we propose that the Rydberg atom-based mixer can be converted to an all-optical phase detector by amplitude modulation(AM)of the LO RF field;that is,the phase of the SIG RF field is related to both the amplitude and phase of the beat signal.When the AM frequency of the LO RF field is the same as the frequency of the beat signal,the beat signal will further interfere with the AM of the LO RF field inside the atom,and then the amplitude of the beat signal is related to the phase of the SIG RF field.The amplitude of the beat signal and the phase of the SIG RF field show a linear relationship within the range of 0 toπ/2 when the phase of the AM is set with a differenceπ/4 from the phase of the LO RF field.The minimum phase resolution can be as small as 0.6°by optimizing the experimental conditions according to a simple theoretical model.This study will expand and contribute to the development of RF measurement devices based on Rydberg atoms.

Design of Digital Multi-Radian Phase Detector on J-TEXT

A real time system used to detect phase difference between two sinusoidal signals is proposed in this paper. The system is designed to process the phase signal of the far-infrared （FIR） hydrogen cyanide （HCN） interferometer on J-TEXT. It is based on zero-crossing detection and makes use of the digital circuit. Compared with a traditional zero-crossing phase detector, it doesn＇t need to sacrifice the time resolution to expand the phase range. The phase difference is divided into two parts, the integer part and the fraction part. In each detecting cycle, they are detected separately. It outputs digital signals that are more stable for transmission. A prototype was built on J-TEXT using discrete components. A practical method is proposed to deal with the counting error caused by the deviation of electronic components in manufacture. Reasonable results were obtained on the prototype. The phase resolution reaches 2π/64 in test, and can still be improved by raising the clock frequency.

Design of IREDM System with a DSP Phase Detector

The design and realization of a new generation of infra-red electronic distance measurement (IR EDM) system are presented.A DSP(Digital Signal Process) phase detector based on high speed analog-to-digital converter and DSP technique has been designed,in order to improve the precision and reliability of IR EDM system.As a result,the EDM system developed with a DSP phase detector has a precision of 3 mm in the measuring range of 2 km.

Passive round-robin differential-quadrature-phase-shift quantum key distribution scheme with untrusted detectors

In this paper, we proposed the scheme for a passive round-robin differential-phase-shift quantum key distribution（RRDPS-QKD） set-up based on the principle of Hong–Ou–Mandel interference. Our scheme requires two legitimate parties to prepare their signal state with two different non-orthogonal bases instead of single in original protocol. Incorporating this characteristic, we establish the level of security of our protocol under the intercept-resend attack and demonstrate its detector-flaw-immune feature. Furthermore, we show that our scheme not only inherits the merit of better tolerance of bit errors and finite-sized-key effects but can be implemented using hardware similar to the measurement device independent QKD（MDI-QKD）. This ensures good compatibility with the current commonly used quantum system.

离子色谱技术研究进展

离子色谱技术作为分析无机离子的首选方法,还可实现小分子极性化合物、氨基酸、糖类等生物样品的分析。近年来,离子色谱技术快速发展,广泛应用在环境监测、食品分析、生物医药、农业、地质等多个领域。针对离子色谱技术的综述多是探讨离子色谱技术在环境、烟草、药品、食品等领域的应用进展,而关注离子色谱技术发展动态的研究报道相对较少。专利文献蕴含科技文献未曾报道的技术研发信息,对于归纳总结前沿技术走向具有重要意义。基于全球范围内离子色谱相关技术专利数据,从淋洗液发生装置、色谱柱固定相、离子色谱抑制器、检测器等方面综述离子色谱分析技术的研究进展,旨为国内离子色谱技术创新发展提供参考与依据。研究表明,全球离子色谱技术研究发展迅速,核心技术及基础研究主要分布在美国和日本,超高压淋洗液发生器、优化供电方式的自动再生电解抑制器及温控稳定的检测器是离子色谱领域新近研究方向,围绕固定相的研究侧重于提高离子交换容量,提高分析速度,改善离子色谱柱效、选择性与亲水性等方面性能。

面向Duobinary信号的时钟恢复电路研究与设计

高速串行接口是高性能计算机系统中芯片之间的互连核心,针对高速串行通信所需高带宽问题,在Candence平台上基于Verilog-AMS完成56 Gbps Duobinary信号时钟数据恢复电路设计与仿真,多电平传输可以减小对带宽的需求。基于相位差值器(PI)设计时钟数据恢复(CDR)电路,以Bang-Bang鉴相器的鉴相结果作为鉴相依据,采用数字信号处理(DSP)算法处理鉴相结果,其包括投票算法、滤波算法以及相位控制码转换算法。数字算法降低了电路设计的复杂度,便于调节环路增益,提高了系统的稳定性,降低环路延迟。仿真结果表明,该CDR电路可以进行相差和100 PPM频差的追踪。对输入数据分别增加0.25 UI正弦抖动,环路带宽为23 MHz,当抖动频率未超过环路带宽时,系统能够跟踪正弦抖动。抖动容限满足CEI-56G协议规范。

A new detector in EBPSK communication system

In order to raise the detection precision of the extended binary phase shift keying （EBPSK） receiver, a detector based on the improved particle swarm optimization algorithm （IMPSO） and the BP neural network is designed. First, the characteristics of EBPSK modulated signals and the special filtering mechanism of the impacting filter are demonstrated. Secondly, an improved particle swarm optimization algorithm based on the logistic chaos disturbance operator and the Cauchy mutation operator is proposed, and the EBPSK detector is designed by utilizing the IMPSO-BP neural network. Finally, the simulation of the EBPSK detector based on the MPSO-BP neural network is conducted and the result is compared with that of the adaptive threshold-based decision, the BP neural network, and the PSO-BP detector, respectively. Simulation results show that the detection performance of the EBPSK detector based on the IMPSO-BP neural network is better than those of the other three detectors.

Automatic IQ Phase Calibration Design in a 2.4GHz Direct Conversion Receiver

An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed. It uses a delay locked loop （DLL） with a proposed quadrature phase detector to greatly reduce the phase error. The receiver is fabricated in a 0.18μm CMOS process. Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.

PLL DEMODULATION TECHNIQUE FOR M-RAY POSITION PHASE SHIFT KEYING

The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.

Phase control system for SSRF linac

The design of phase control system in Shanghai Synchrotron Radiation Facility (SSRF) linac is presented in this paper. And digital phase detecting algorithm, the key for phase control system, is fully described. The testing results for phase control system in 100MeV linac are discussed in detail.

IDENTIFICATION OF PHASE ERROR BY MULTI-SAMPLING DIGITAL TANLOCKED LOOP(MS-DTL)

A multisampling technique was introduced to the phase error detector of Conventional Digital Tanlocked Loop(C DTL). In this new technique a number of samples ( M ) were taken at nonuniform intervals within one period of the input signal. The novel system is called Multisampling Digital Tanlocked loop(MS DTL). The simulated model on the computer shows that for M =4, the system has a faster locking speed and wider locking in range compared with C DTL.

Study and ICH validation of a reverse-phase liquid chromatographic method for the quantification of the intact monoclonal antibody cetuximab

Cetuximab （CTX） is a potent chimeric mouse/human monoclonal antibody （mAb） approved worldwide for treatment of metastatic colorectal cancer. Among the various biological and physical analyses per- formed for full study on this biopharmaceutic, the determination of the concentration preparations throughout manufacturing and subsequent handling in hospital is particularly relevant. In the present work, the study and validation of a method for quantifying intact CTX by reverse-phase high-perfor- mance liquid chromatography with diode array detection （（RP）HPLC/DAD） is presented. With that end, we checked the performance of a chromatographic method for quantifying CTX and conducted a study to validate the method as stability-indicating in accordance with the International Conference on Harmo- nization guidelines （ICH） for biotechnological drugs; therefore, we evaluated linearity, accuracy, preci- sion, detection and quantification limits, robustness and system suitability. The specificity of the method and the robustness of the mAb formulation against external stress factors were estimated by compre- hensive chromatographic analysis by subjecting CTX to several informative stress conditions. As de- monstrated, the method is rapid, accurate, and reproducible for CTX quantification. It was also suc- cessfully used to quantify CTX in a long-term stability study performed under hospital conditions.

Extraction and Determination of Three Chlorophenols by Hollow Fiber Liquid Phase Microextraction - Spectrophotometric Analysis, and Evaluation Procedures Using Mean Centering of Ratio Spectra Method

A method termed hollow fiber liquid phase microextraction (HF-LPME) was utilized to extract three chlo- rophenols, 2-chlorophenol (2-CP), 2,4-dichlorophenol (2,4-DCP) and 2,4,6- trichlorophenol (2,4,6-TCP), separately from water. The extracted chlorophenols were then separated, identified, and quantified by UV-Vis spectrophotometry with photodiode array detection (UV-Vis/DAD). In the study, experimental con-ditions such as organic phase identity, acceptor phase volume, sample agitation, extraction time, acceptor phase NaOH concentration, donor phase HCl concentration, salt addition, and UV absorption wavelength were optimized. The statistical parameters of the proposed method were investigated under the selected con-ditions. The analytical characteristics of the method such as detection limit, accuracy, precision, relative standard deviation (R.S.D.) and relative standard error (R.S.E.) was calculated. The results showed that the proposed method is simple, rapid, accurate and precise for the analysis of ternary mixtures.

SYMMETRIC INFORMATION RATE OF CPM AND OPTIMAL DETECTOR DESIGN

This paper first calculates numerically the Symmetric Information Rate (SIR) of Cotinuous Phase Modulation (CPM) schemes over Additive White Gaussian Noise (AWGN) channel, modeling CPM and channel as a Memory-less Modulator (MM) plus a Markov Finite State Channel (FSMC), then proposes an optimal detector, which is of BCJR based Decision Feedback Detector (DFD) but non-iterative. It can achieve the SIR as the sequence length approaches infinity while the complexity is extremely low. Finally, both theoretic proof and numerical simulation are performed to show the op- timality. Simulation results show that it nearly achieves the theoretic bound and outperforms the Viterbi Detector (VD) with 2dB in low Eb/N0.

一种适用于亚采样锁相环的高鲁棒性辅助锁定电路

当前的研究表明,基于亚采样相位检测器(Sub-Sampling Phase Detectors,SSPD)的锁相环(Phase-Locked Loop,PLL)相较传统锁相环架构可以实现显著降低的带内相位噪声。然而,在片上系统(Systems on Chip,SOCs)应用中,PLL容易受到衬底或电源耦合的干扰,这很可能会导致PLL失去锁定,且可能无法恢复。针对此问题,提出一种将辅助锁频环(Frequency-Locked Loop,FLL)和数字锁定检测器(Digital Lock Detector,DLD)相结合的适用于亚采样锁相环(Sub-Sampling Phase-Locked Loop,SSPLL)的高鲁棒性辅助锁定电路。仿真结果表明:与传统SSPLL相比,所提出的电路极大提升了PLL对衬底或电源干扰的鲁棒性,同时保持了其低相位噪声的优点,这对于SSPLL在大规模生产和应用中的可靠性具有重要意义。

低抖动电荷泵锁相环设计及其Simulink建模仿真

随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。