A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Low cost, practical, all-digital open-loop fiber-optic gyroscope

A novel all-digital scheme for open-loop fiber-optic gyroscope (POG), where only two key points of output wave were digitized directly, has been proposed. A control equation, with which the modulation depth of PZT modulator is stable when setting the modulation depth as 4.35 and a calculation equation, with which the Sagnac phase can be worked out, are derived. A modulation depth control and an automatic correlation sampling and a gain control technology were induced. A photo-type FOG was made and tested. The good performance was achieved.

ASIC Design of M13

The MX3101 E3/E1 Multiplexer/Demultiplexer(M13)device with digital cross-connec-tors is the first industrial semiconductor chip which can provide the whole circuitry neededfor a complete plesiochronous E3/E1 multiplexer/demultiplexer on a single CMOS VLSI de-vice.By a novel all-digital phase-locked loop(PLL)and a timing regeneration circuit,thewhole system is integrated on a LSILogic’s LCA405K gate array ASIC with 50K gates and144 pins.

A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy

In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC.The SAR ADC has a chip area of 2.7×2.4 mm^2,and consumes only 100μW at the 2.5 V supply voltage with 100 KSPS.The INL and DNL are both less than 0.5 LSB.

An all-digital synthesizable baseband for a delay-based LINC transmitter with reconfigurable resolution

The linear amplification with nonlinear component transmitter is a promising solution to high efficiency and high linearity amplification for non-constant envelope signals. An all-digital synthesizable baseband for a delay-based LINC transmitter is implemented. This paper proposes a standard-cell based synthesizable methodology which can be applied in the ASIC process efficiently without performance degradation compared to the manual layout. A scheme to overcome the limited resolution of conventional phase detectors is proposed. It employs alter- native phase detector structures to provide reconfigurability for higher resolution after fabricating, resulting in an 11 ps resolution improvement. Due to the PVT variation, an adaptive calibration scheme focusing on the inherent imbalance between two delay lines is depicted, which reveals an effective EVM enhancement of 5.37 dB. This baseband chip is implemented in 0.13 μm CMOS technology, and the transmitter with the baseband has an EVM of-28.96 dB and an ACPR of-29.51 dB, meeting the design requirement.

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.

Research on crystal growth and properties of a new nonlinear optical crystal:Bismuth borate BiB_3O_6

BiB3O6 (BIBO) single crystals with sizes of 44 mm × 24 mm × 10 mm and weight of 24.7 g have been successfully grown by the top-seeded method. In this note, the preparation of seed, the growth of crystal and some problems encountered are reported. The lattice parameters of BIBO are a =7.1203(7)A, b = 4.9948(7)A, c = 6.5077(7)A, β= 105.586(8) ", V=222.93(5)A3, which were determined by BRUKER-P4 four-circle diffractometer. BIBO is biaxial crystal and the relative orientation of (X, Y, Z) with regard to (a, b, c) is: X|| b, (Y, c) =47.2°, (Z, a) = 31.6°, determined by the X-ray analysis combined with polarized microscopy. The second-harmonic-generation (SHG) conversion efficiency of the sample for 1.064 μm light is up to 67.7%. We have also obtained the third harmonic generation (THG) of 1.064 μm, namely, 1.064 μm + 0.532 μn →0.355 μm. BIBO crystal is free of moisture and hygroscopy.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

A high-accuracy DCO with hybrid architecture

In this paper, a novel hybrid digital-controlled oscillator（DCO） is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts： DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature（PVT） variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm^2 chip area. The output frequency is adjusted from 15–120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6–1.8 V supply voltage and 0–80℃ temperature variations in TT, FF,SS corners.