The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transisto...The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.展开更多
In this work, a method based on scanning Kelvin probe microscopy is proposed to separately extract source/drain（S/D） series resistance in operating amorphous indium–gallium–zinc–oxide（a-IGZO） thin-film transist...In this work, a method based on scanning Kelvin probe microscopy is proposed to separately extract source/drain（S/D） series resistance in operating amorphous indium–gallium–zinc–oxide（a-IGZO） thin-film transistors. The asymmetry behavior of S/D contact resistance is deduced and the underlying physics is discussed. The present results suggest that the asymmetry of S/D contact resistance is caused by the difference in bias conditions of the Schottky-like junction at the contact interface induced by the parasitic reaction between contact metal and a-IGZO. The overall contact resistance should be determined by both the bulk channel resistance of the contact region and the interface properties of the metalsemiconductor junction.展开更多
Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we ex...Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.展开更多
Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-...Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.展开更多
The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light e...The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.展开更多
针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟...针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟研究态密度关键参数对器件性能的影响,以此揭示a-IGZO TFTs中制备工艺对导电沟道修复的物理机理.首先,采用结合强度较高的钼/铜双层结构作为栅/源/漏电极,引入BCE方法制备了底栅顶接触(BottomGate Top-Contact,BG-TC)TFTs.其次,建立了适用于BCE技术的a-IGZO TFTs的HCD-DOS模型.随后,基于TCAD(Technology Computer Aided Design)仿真器对态密度关键参数进行数值研究,结果表明,不同态密度参数对a-IGZO TFTs器件转移特性曲线、电学特性以及沟道内部电子浓度分布的影响有所差异.最后,基于HCD-DOS模型探索SiO_(x)钝化层沉积和N_(2)O等离子体处理对器件内部机理的影响.研究发现,N2O等离子体处理对态密度分布和沟道载流子浓度有显著影响,进而导致阈值电压正向漂移.展开更多
基金Project supported by the National Basic Research Program of China(Grant Nos.2011CB301900 and 2011CB922100)the Priority Academic Program Development of Jiangsu Higher Education Institutions,China
文摘The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.
基金Project supported by the Key Industrial R&D Program of Jiangsu Province,China(Grant No.BE2015155)the Priority Academic Program Development of Higher Education Institutions of Jiangsu Province,Chinathe Fundamental Research Funds for the Central Universities,China(Grant No.021014380033)
文摘In this work, a method based on scanning Kelvin probe microscopy is proposed to separately extract source/drain（S/D） series resistance in operating amorphous indium–gallium–zinc–oxide（a-IGZO） thin-film transistors. The asymmetry behavior of S/D contact resistance is deduced and the underlying physics is discussed. The present results suggest that the asymmetry of S/D contact resistance is caused by the difference in bias conditions of the Schottky-like junction at the contact interface induced by the parasitic reaction between contact metal and a-IGZO. The overall contact resistance should be determined by both the bulk channel resistance of the contact region and the interface properties of the metalsemiconductor junction.
基金Supported by the National Natural Science Foundation of China under Grant No 61574048the Science and Technology Research Project of Guangdong Province under Grant Nos 2015B090912002 and 2015B090901048the Pearl River S&T Nova Program of Guangzhou under Grant No 201710010172
文摘Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.
基金Project supported by the Science and Technology Program of Suzhou City,China(Grant No.SYG201538)the National Natural Science Foundation of China(Grant No.61574096)
文摘Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.
基金supported by the State Key Program for Basic Research of China(Grant Nos.2011CB301900 and 2011CB922100)the Priority Academic Program Development of Higher Education Institutions of Jiangsu Province,China
文摘The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.
文摘针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟研究态密度关键参数对器件性能的影响,以此揭示a-IGZO TFTs中制备工艺对导电沟道修复的物理机理.首先,采用结合强度较高的钼/铜双层结构作为栅/源/漏电极,引入BCE方法制备了底栅顶接触(BottomGate Top-Contact,BG-TC)TFTs.其次,建立了适用于BCE技术的a-IGZO TFTs的HCD-DOS模型.随后,基于TCAD(Technology Computer Aided Design)仿真器对态密度关键参数进行数值研究,结果表明,不同态密度参数对a-IGZO TFTs器件转移特性曲线、电学特性以及沟道内部电子浓度分布的影响有所差异.最后,基于HCD-DOS模型探索SiO_(x)钝化层沉积和N_(2)O等离子体处理对器件内部机理的影响.研究发现,N2O等离子体处理对态密度分布和沟道载流子浓度有显著影响,进而导致阈值电压正向漂移.
