Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.

The Electric Vehicle Surge:Effective Solutions for Charging Challenges with Advanced Converter Technologies

The global adoption of Electric Vehicles(EVs)is on the rise due to their advanced features,with projections indicating they will soon dominate the private vehicle market.However,improper management of EV charging can lead to significant issues.This paper reviews the development of high-power,reliable charging solutions by examining the converter topologies used in rectifiers and converters that transfer electricity from the grid to EV batteries.It covers technical details,ongoing developments,and challenges related to these topologies and control strategies.The integration of rapid charging stations has introduced various Power Quality(PQ)issues,such as voltage fluctuations,harmonic distortion,and supra-harmonics,which are discussed in detail.The paper also highlights the benefits of controlled EV charging and discharging,including voltage and frequency regulation,reactive power compensation,and improved power quality.Efficient energy management and control strategies are crucial for optimizing EV battery charging within microgrids to meet increasing demand.Charging stations must adhere to specific converter topologies,control strategies,and industry standards to function correctly.The paper explores microgrid architectures and control strategies that integrate EVs,energy storage units(ESUs),and Renewable Energy Sources(RES)to enhance performance at charging points.It emphasizes the importance of various RES-connected architectures and the latest power converter topologies.Additionally,the paper provides a comparative analysis of microgrid-based charging station architectures,focusing on energy management,control strategies,and charging converter controls.The goal is to offer insights into future research directions in EV charging systems,including architectural considerations,control factors,and their respective advantages and disadvantages.

A Novel Control Strategy Based onπ-VSG for Inter-Face Converter in Hybrid Microgrid

The rapid development of new energy power generation technology and the transformation of power electronics in the core equipment of source-grid-load drives the power system towards the“double-high”development pattern of“high proportion of renewable energy”and“high proportion of power electronic equipment”.To enhance the transient performance of AC/DC hybrid microgrid(HMG)in the context of“double-high,”aπtype virtual synchronous generator(π-VSG)control strategy is applied to bidirectional interface converter(BIC)to address the issues of lacking inertia and poor disturbance immunity caused by the high penetration rate of power electronic equipment and new energy.Firstly,the virtual synchronous generator mechanical motion equations and virtual capacitance equations are used to introduce the virtual inertia control equations that consider the transient performance of HMG;based on the equations,theπ-type equivalent control model of the BIC is established.Next,the inertia power is actively transferred through the BIC according to the load fluctuation to compensate for the system’s inertia deficit.Secondly,theπ-VSG control utilizes small-signal analysis to investigate howthe fundamental parameters affect the overall stability of the HMG and incorporates power step response curves to reveal the relationship between the control’s virtual parameters and transient performance.Finally,the PSCAD/EMTDC simulation results show that theπ-VSG control effectively improves the immunity of AC frequency and DC voltage in the HMG system under the load fluctuation condition,increases the stability of the HMG system and satisfies the power-sharing control objective between the AC and DC subgrids.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Recent advancements in continuously scalable conversion-ratio switched-capacitor converter

Switched-capacitor(SC)DC-DC converter[1]is an impor-tant alternative to inductive DC-DC converter,in terms of removing the bulky power inductor.Hence,it is widely used in low-profile,low-power applications,such as the internet of things(IoT)sensor nodes and energy harvesting[2].Mean-while,considering that capacitor has a much higher energy density than inductor,high-power applications.

Modeling the System for Hybrid Renewable Energy Using Highly Efficient Converters and Generator

High-efficient isolated DC/DC converters with a high-efficiency synchronous reluctance generator(SRG)are the ultimate solutions in DC microgrid systems.The design and modeling of isolated DC/DC converters with the performance of SRG are carried out.On the generator side,reactive and active powers are used as pulse width modulation(PWM)control variables.Further,the flux estimator is used.Three-phase PWM rectifier is used by applying space vector modulation(SVM)with a constant switching frequency for direct power control.Further,the paper also includes the experimental validation of the results.The paper also proposes that highly efficient power converters and synchronous reluctance generators are required to achieve high performance for hybrid renewable energy systems applications.

A real-time calibration method based on time-to-digital converter for accelerator timing system

The high-intensity heavy-ion accelerator facility(HIAF)is a scientific research facility complex composed of multiple cas-cade accelerators of different types,which pose a scheduling problem for devices distributed over a certain range of 2 km,involving over a hundred devices.The white rabbit,a technology-enhancing Gigabit Ethernet,has shown the capability of scheduling distributed timing devices but still faces the challenge of obtaining real-time synchronization calibration param-eters with high precision.This study presents a calibration system based on a time-to-digital converter implemented on an ARM-based System-on-Chip(SoC).The system consists of four multi-sample delay lines,a bubble-proof encoder,an edge controller for managing data from different channels,and a highly effective calibration module that benefits from the SoC architecture.The performance was evaluated with an average RMS precision of 5.51 ps by measuring the time intervals from 0 to 24,000 ps with 120,000 data for every test.The design presented in this study refines the calibration precision of the HIAF timing system.This eliminates the errors caused by manual calibration without efficiency loss and provides data support for fault diagnosis.It can also be easily tailored or ported to other devices for specific applications and provides more space for developing timing systems for particle accelerators,such as white rabbits on HIAF.

Robust optical mode converter based on topological waveguide arrays

Optical mode converters are essential for enhancing the capacity of optical communication systems. However, fabrication errors restrict the further improvement of conventional mode converters. To address this challenge, we have designed an on-chip TE0–TE1mode converter based on topologically protected waveguide arrays. The simulation results demonstrate that the converter exhibits a mode coupling efficiency of 93.5% near 1550 nm and can tolerate a relative fabrication error of 30%. Our design approach can be extended to enhance the robustness for other integrated photonic devices, beneficial for future development of optical network systems.

Energy-Efficient Implementation of BCD to Excess-3 Code Converter for Nano-Communication Using QCA Technology

Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique was adopted to investigate integration with other complicated circuits.Using a unique XOR gate,the recommended circuit’s cell complexity has been decreased.The findings produced using the QCADesigner-2.0.3,a reliable simulation tool,prove the effectiveness of the current structure over earlier designs by considering the number of cells deployed,the area occupied,and the latency as design metrics.In addition,the popular tool QCAPro was used to estimate the energy dissipation of the proposed design.The proposed technique reduces the occupied space by∼40%,improves cell complexity by∼20%,and reduces energy dissipation by∼1.8 times(atγ=1.5EK)compared to the current scalable designs.This paper also studied the suggested structure’s energy dissipation and compared it to existing works for a better performance evaluation.

Modular System of Cascaded Converters Based on Model Predictive Control

A modular system of cascaded converters based on model predictive control(MPC)is proposed to meet the application requirements ofmultiple voltage levels and electrical isolation in renewable energy generation systems.The system consists of a Buck/Boost+CLLLC cascaded converter as a submodule,which is combined in series and parallel on the input and output sides to achieve direct-current(DC)voltage transformation,bidirectional energy flow,and electrical isolation.The CLLLC converter operates in DC transformer mode in the submodule,while the Buck/Boost converter participates in voltage regulation.This article establishes a suitable mathematical model for the proposed system topology,and uses MPC to control the system based on this mathematical model.Module parameters are designed and calculated,and simulation is built in MATLAB/Simulink to complete the simulation comparison experiment between MPC and traditional proportional integral(PI)control.Finally,a physical experimental platform is built to complete the physical comparison experiment.The simulation and physical experimental results prove that the control accuracy and response speed ofMPC are better than traditional PI control strategy.

Hydrodynamic Performance of An Integrated System of Breakwater and A Multi-Chamber OWC Wave Energy Converter

A multi-chamber oscillating water column wave energy converter(OWC-WEC)integrated to a breakwater is investigated.The hydrodynamic characteristics of the device are analyzed using an analytical model based on the linear potential flow theory.A pneumatic model is employed to investigate the relationship between the air mass flux in the chamber and the turbine characteristics.The effects of chamber width,wall draft and wall thickness on the hydrodynamic performance of a dual-chamber OWC-WEC are investigated.The results demonstrate that the device,with a smaller front wall draft and a wider rear chamber exhibits a broader effective frequency bandwidth.The device with a chamber-width-ratio of 1:3 performs better in terms of power absorption.Additionally,results from the analysis of a triplechamber OWC-WEC demonstrate that reducing the front chamber width and increasing the rearward chamber width can improve the total performance of the device.Increasing the number of chambers from 1 to 2 or 3 can widen the effective frequency bandwidth.

Design Method of Anti-Total Ionizing Dose Effect Hardening for Buck-Boost Converter

Buck-Boost converter in the total dose radiation environment will mainly bring the output voltage drift, linear adjustment rate and load adjustment rate decline and other effects, so that the output stability performance of the circuit deteriorates. Aiming at the problems of high cost,large layout area and poor universality caused by the traditional total ionizing dose effect hardening method based on process and layout, this paper proposes a total ionizing dose effect hardening design method with parallel monitoring and hardening, which can achieve total ionizing dose effect hardening at the circuit level without process. The anti-total dose capability of Buck-Boost converter is improved. The circuit design and physical implementation of the proposed method are verified based on 0.18 μm bipolar complementary metal-oxide-semiconductor(CMOS) double-diffused metal-oxide-semiconductor(DMOS)(BCD) process. The results show that the system gain decrease rate can be compensated from 19.2% to 6.2%, and the output voltage shift rate can be improved from 2.00% to 0.15% at a dose of 200×10^(3) rad(Si). Moreover, the load adjustment rate and linear adjustment rate are reduced. They are respectively decreased to 0.191 %/A and 0.093 %/V. This provides a new idea for the design of total ionizing dose effect hardening at circuit and system level.

Negative Stiffness Mechanism on An Asymmetric Wave Energy Converter by Using A Weakly Nonlinear Potential Model

Salter's duck,an asymmetrical wave energy converter(WEC)device,showed high efficiency in extracting energy from 2D regular waves in the past;yet,challenges remain for fluctuating wave conditions.These can potentially be addressed by adopting a negative stiffness mechanism(NSM)in WEC devices to enhance system efficiency,even in highly nonlinear and steep 3D waves.A weakly nonlinear model was developed which incorporated a nonlinear restoring moment and NSM into the linear formulations and was applied to an asymmetric WEC using a time domain potential flow model.The model was initially validated by comparing it with published experimental and numerical computational fluid dynamics results.The current results were in good agreement with the published results.It was found that the energy extraction increased in the range of 6%to 17%during the evaluation of the effectiveness of the NSM in regular waves.Under irregular wave conditions,specifically at the design wave conditions for the selected test site,the energy extraction increased by 2.4%,with annual energy production increments of approximately 0.8MWh.The findings highlight the potential of NSM in enhancing the performance of asymmetric WEC devices,indicating more efficient energy extraction under various wave conditions.

Harmonic Impedance Modeling and Oscillation Analysis of Modular Multilevel Converter

To facilitate rapid analysis of the oscillation stability mechanism in modular multilevel converter-based high voltage direct current(MMC-HVDC)systems and streamline the simulation process for determining MMC impedance characteristics,a simplified mathematical simulation model for MMC closed-loop impedance is developed using the harmonic state space method.This model considers various control strategies and includes both AC-side and DC-side impedance models.By applying a Nyquist criterion-based impedance analysis method,the stability mechanisms on the AC and DC sides of the MMC are examined.In addition,a data-driven oscillation stability analysis method is also proposed,leveraging a global sensitivity algorithm based on fast model results to identify key parameters influencing MMC oscillation stability.Based on sensitivity analysis results,a parameter adjustment strategy for oscillation suppression is proposed.The simulation results from the MATLAB/Simulinkbased MMC model validate the effectiveness of the proposed method.