This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)tr...This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.展开更多
The analog-to-information convertor (AIC) is a successful practice of compressive sensing (CS) theory in the analog signal acquisition. This paper presents a multi-narrowband signals sampling and reconstruction model ...The analog-to-information convertor (AIC) is a successful practice of compressive sensing (CS) theory in the analog signal acquisition. This paper presents a multi-narrowband signals sampling and reconstruction model based on AIC and block sparsity. To overcome the practical problems, the block sparsity is divided into uniform block and non-uniform block situations, and the block restricted isometry property and sub-sampling limit in different situations are analyzed respectively in detail. Theoretical analysis proves that using the block sparsity in AIC can reduce the restricted isometric constant, increase the reconstruction probability and reduce the sub -sampling rate. Simulation results show that the proposed model can complete sub -sampling and reconstruction for multi-narrowband signals. This paper extends the application range of AIC from the finite information rate signal to the multi-narrowband signals by using the potential relevance of support sets. The proposed receiving model has low complexity and is easy to implement, which can promote the application of CS theory in the radar receiver to reduce the burden of analog-to digital convertor (ADC) and solve bandwidth limitations of ADC.展开更多
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr...The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.展开更多
Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is cons...Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.展开更多
This paper extends the application of compressive sensing(CS) to the radar reconnaissance receiver for receiving the multi-narrowband signal. By combining the concept of the block sparsity, the self-adaption methods, ...This paper extends the application of compressive sensing(CS) to the radar reconnaissance receiver for receiving the multi-narrowband signal. By combining the concept of the block sparsity, the self-adaption methods, the binary tree search,and the residual monitoring mechanism, two adaptive block greedy algorithms are proposed to achieve a high probability adaptive reconstruction. The use of the block sparsity can greatly improve the efficiency of the support selection and reduce the lower boundary of the sub-sampling rate. Furthermore, the addition of binary tree search and monitoring mechanism with two different supports self-adaption methods overcome the instability caused by the fixed block length while optimizing the recovery of the unknown signal.The simulations and analysis of the adaptive reconstruction ability and theoretical computational complexity are given. Also, we verify the feasibility and effectiveness of the two algorithms by the experiments of receiving multi-narrowband signals on an analogto-information converter(AIC). Finally, an optimum reconstruction characteristic of two algorithms is found to facilitate efficient reception in practical applications.展开更多
基金This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.
文摘This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.
基金supported by the National Natural Science Foundation of China(61172159)
文摘The analog-to-information convertor (AIC) is a successful practice of compressive sensing (CS) theory in the analog signal acquisition. This paper presents a multi-narrowband signals sampling and reconstruction model based on AIC and block sparsity. To overcome the practical problems, the block sparsity is divided into uniform block and non-uniform block situations, and the block restricted isometry property and sub-sampling limit in different situations are analyzed respectively in detail. Theoretical analysis proves that using the block sparsity in AIC can reduce the restricted isometric constant, increase the reconstruction probability and reduce the sub -sampling rate. Simulation results show that the proposed model can complete sub -sampling and reconstruction for multi-narrowband signals. This paper extends the application range of AIC from the finite information rate signal to the multi-narrowband signals by using the potential relevance of support sets. The proposed receiving model has low complexity and is easy to implement, which can promote the application of CS theory in the radar receiver to reduce the burden of analog-to digital convertor (ADC) and solve bandwidth limitations of ADC.
基金Supported by the CAS/SAFEA International Partnership Program for Creative Research Teams,National High Technology Research and Develop Program of China(2012AA012301)National Science and Technology Major Project of China(2013ZX03006004)
文摘The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.
基金supported in part by the National Natural Science Foundation of China(No.61601027)the Opening Fund of the Space Objective Measure Key Laboratory(No.2016011)
文摘Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.
基金supported by the National Natural Science Foundation of China(61172159)
文摘This paper extends the application of compressive sensing(CS) to the radar reconnaissance receiver for receiving the multi-narrowband signal. By combining the concept of the block sparsity, the self-adaption methods, the binary tree search,and the residual monitoring mechanism, two adaptive block greedy algorithms are proposed to achieve a high probability adaptive reconstruction. The use of the block sparsity can greatly improve the efficiency of the support selection and reduce the lower boundary of the sub-sampling rate. Furthermore, the addition of binary tree search and monitoring mechanism with two different supports self-adaption methods overcome the instability caused by the fixed block length while optimizing the recovery of the unknown signal.The simulations and analysis of the adaptive reconstruction ability and theoretical computational complexity are given. Also, we verify the feasibility and effectiveness of the two algorithms by the experiments of receiving multi-narrowband signals on an analogto-information converter(AIC). Finally, an optimum reconstruction characteristic of two algorithms is found to facilitate efficient reception in practical applications.
