A survey of high-speed high-resolution current steering DACs

Digital to analog converters(DAC)play an important role as a bridge connecting the analog world and the digital world.With the rapid development of wireless communication,wideband digital radar,and other emerging technologies,better performing high-speed high-resolution DACs are required.In those applications,signal bandwidth and high-frequency linearity often limited by data converters are the bottleneck of the system.This article reviews the state-of-the-art technologies of high-speed and high-resolution DACs reported in recent years.Comparisons are made between different architectures,circuit implementations and calibration techniques along with the figure of merit(FoM)results.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.

A 12-bit 80 MS/s 2 mW SAR ADC with Deliberated Digital Calibration and Redundancy Schemes for Medical Imaging

In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency.A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit.The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of>10.5 bit equivalent number of bits(ENOB),<±1 least significant bit(LSB)differential nonlinearity(DNL)&integrated nonlinearity(INL),while only consuming less than 2 mA current from a 1.1 V power supply.The calculated figure of merit(FoM)is 17.4 fJ/conversion-step.This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.