A test strategy for analog filters was proposed. The output voltage and supply current of the circuit were monitored when using the oscillation test technique. The frequency, average value, maximum value and amplitude...A test strategy for analog filters was proposed. The output voltage and supply current of the circuit were monitored when using the oscillation test technique. The frequency, average value, maximum value and amplitude of both output voltage and supply current were taken as test parameters. Tolerance bands of test parameters were analyzed. Fault detectabilities of test parameters were compared and combined, and optimal parameter sets were derived. Experimental results show that both the output voltage and supply current give significant contribution to fault detection. Considering catastrophic, single and double parametric faults, the fault coverage in testing the benchmark circuit can be raised from 90.6% for traditional voltageonly oscillation test strategy to 97.2% by monitoring both output voltage and current parameters.展开更多
A new multi function voltage-mode universal biquadratic filter using single Voltage Differencing Differential Input Buffered Amplifier (VD-DIBA), two capacitors and one resistor is proposed. The proposed configuration...A new multi function voltage-mode universal biquadratic filter using single Voltage Differencing Differential Input Buffered Amplifier (VD-DIBA), two capacitors and one resistor is proposed. The proposed configuration has four inputs and one output and can realize all the five standard filters from the same circuit configuration. The presented biquad filter offers low active and passive sensitivities. The validity of proposed universal biquadratic filter has been verified by SPICE simulation using 0.35 μm MIETEC technology.展开更多
A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the...A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the five standard biquadratic filters: low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) from the same circuit configuration. The presented universal filter offers low active and passive sensitivities. SPICE (Version 16.5) simulation results using 0.18 μm TSMC technology have been included.展开更多
This paper presents a novel leapfrog signal flow graph (SFG) implementation by fully differential Op amp integrators, which combines low sensitivity, high dynamic range with simple circuit configuration. The direct SF...This paper presents a novel leapfrog signal flow graph (SFG) implementation by fully differential Op amp integrators, which combines low sensitivity, high dynamic range with simple circuit configuration. The direct SFG simulation and leapfrog SFG simulation can yield integrator-based structures likewise, but both of them will lead to higher circuit complexity, noise density and sensitivity. Three Butterworth 5-order high-pass filters with a pass band edge frequency of 1.778 kHz are designed based on different SFGs. From the example, the noise density of the simplest leapfrog configuration is approximately 0.4 nV/Hz1/2 lower than those of the other two in the stop band, and shows the best noise density in the pass band. The sensitivity densities of two types of leapfrog filters are approximately equivalent, while that of the direct SFG simulation filter is much higher. However, the pass band response of the simplest configuration is not as good as those of the other two because of two parasitic zeros (at 708 kHz, -31.6 dB and 1.59 MHz, -20.55 dB) and a parasitic pole (at 4.57 MHz, 45.5 dB).展开更多
A novel four-input three-output voltage-mode differential difference current conveyor (DDCC) based universal filter is presented. The circuit uses three DDCCs as active elements, two resistors and two capacitors as pa...A novel four-input three-output voltage-mode differential difference current conveyor (DDCC) based universal filter is presented. The circuit uses three DDCCs as active elements, two resistors and two capacitors as passive elements. The circuit along with its versatility enjoys the advantage of minimum number of passive elements employment. SPICE simulation results are given to confirm the theoretical analysis. The proposed circuit is a novel addition to the existing knowledge on the subject.展开更多
This paper proposes an nth order (where n = 2,3, ,n) voltage mode active-C filter using n number of current controlled current conveyors (CCCIIs) and n number of equal valued grounded capacitors. The proposed topology...This paper proposes an nth order (where n = 2,3, ,n) voltage mode active-C filter using n number of current controlled current conveyors (CCCIIs) and n number of equal valued grounded capacitors. The proposed topology can implement both band pass and low pass responses without alteration of any components. The filters offer the following important features: use of minimum number of current controlled current conveyors (CCCIIs) and passive components, no matching constraint, use of all grounded capacitors and absence of external resistor suitable for integration, cut off frequency can easily be electronically adjusted using AMS 0.35 μm CMOS technology. PSPICE simulation results of third order band pass and low pass responses are provided. The results are found to agree well with the theory.展开更多
In this paper, an application of voltage differencing voltage transconductance amplifier (VDVTA) in the realization of voltage-mode (VM) multi-input single output (MISO) type biquad is presented. The proposed topology...In this paper, an application of voltage differencing voltage transconductance amplifier (VDVTA) in the realization of voltage-mode (VM) multi-input single output (MISO) type biquad is presented. The proposed topology uses one VDVTA as an active element, two capacitors and a grounded resistor. The configuration realizes low pass (LP), high pass (HP), band pass (BP) and notch (BR) filters without the requirement of any matching condition. The natural frequency (w0) and bandwidth (BW) are independently controllable. The proposed circuit offers low active and passive sensitivities of w0. The operation of the proposed circuit has been verified through SPICE simulation with TSMC CMOS 0.18 μm process parameters.展开更多
Two new current mode active-RC networks using the second generation current conveyer (CCII) devices are presented. The circuits provide high-Q bandpass (BP)/lowpass(LP) filter characteristics; the highpass(HP) respons...Two new current mode active-RC networks using the second generation current conveyer (CCII) devices are presented. The circuits provide high-Q bandpass (BP)/lowpass(LP) filter characteristics; the highpass(HP) response may also be obtained with suitable design. Current mode sine wave signal generation (Q→α) is possible by tuning a grounded resistor. With non-ideal CCIIs the design equations are slightly altered owing to CCII port current and voltage tracking errors (Ei,v).展开更多
This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplif...This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA). The proposed filter provides the following important and desirable features: (i) One can use only one CCDDCCTA and two capacitors;(ii) One can get low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) current responses from the same configuration without any alteration;(iii) Passive components are grounded, which ease the integrated circuit implementation;(iv) Responses are electronically tunable;and (v) Sensitivity is low. Moreover, the non-ideality analysis shows that the parasitic passive components can be compensated for the proposed circuit. The functionality of the design is verified through SPICE simulations using 0.25 μm CMOS TSMC technology process parameters. Simulation result agrees well with the theoretical analysis.展开更多
The paper presents a new universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors. The offered structure has three inputs and one output and can realise all the five...The paper presents a new universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors. The offered structure has three inputs and one output and can realise all the five basic biquadratic filters: high-pass (HP), low-pass (LP), band-reject (BR), band-pass (BP) and all-pass (AP) from the same circuit topology. The proposed universal filter also provides following advantageous features, not available simultaneously in any UVC based universal biquadratic filter so far: (i) low active and passive sensitivities, (ii) independent control of natural frequency (ω0) and bandwidth (BW) and (iii) no requirement of any component matching condition and inversion of input signal(s) (as needed in most of the earlier reported structures). The workability of proposed structure has been presented by SPICE (Version 16.5) simulation using 0.18 μm TSMC technology.展开更多
A binary tree representation is designed in this paper for optimization of wave digital filter(WDF)implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree represen...A binary tree representation is designed in this paper for optimization of wave digital filter(WDF)implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array(FPGA)resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.展开更多
基金the National Key Basic Research and Development (973) Program of China(No. 2005CB321604)the National Natural Science Foundation of China (No. 60633060)
文摘A test strategy for analog filters was proposed. The output voltage and supply current of the circuit were monitored when using the oscillation test technique. The frequency, average value, maximum value and amplitude of both output voltage and supply current were taken as test parameters. Tolerance bands of test parameters were analyzed. Fault detectabilities of test parameters were compared and combined, and optimal parameter sets were derived. Experimental results show that both the output voltage and supply current give significant contribution to fault detection. Considering catastrophic, single and double parametric faults, the fault coverage in testing the benchmark circuit can be raised from 90.6% for traditional voltageonly oscillation test strategy to 97.2% by monitoring both output voltage and current parameters.
文摘A new multi function voltage-mode universal biquadratic filter using single Voltage Differencing Differential Input Buffered Amplifier (VD-DIBA), two capacitors and one resistor is proposed. The proposed configuration has four inputs and one output and can realize all the five standard filters from the same circuit configuration. The presented biquad filter offers low active and passive sensitivities. The validity of proposed universal biquadratic filter has been verified by SPICE simulation using 0.35 μm MIETEC technology.
文摘A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the five standard biquadratic filters: low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) from the same circuit configuration. The presented universal filter offers low active and passive sensitivities. SPICE (Version 16.5) simulation results using 0.18 μm TSMC technology have been included.
基金Supported by Youth Research Fund of Naval Aeronautical Engineering Institute
文摘This paper presents a novel leapfrog signal flow graph (SFG) implementation by fully differential Op amp integrators, which combines low sensitivity, high dynamic range with simple circuit configuration. The direct SFG simulation and leapfrog SFG simulation can yield integrator-based structures likewise, but both of them will lead to higher circuit complexity, noise density and sensitivity. Three Butterworth 5-order high-pass filters with a pass band edge frequency of 1.778 kHz are designed based on different SFGs. From the example, the noise density of the simplest leapfrog configuration is approximately 0.4 nV/Hz1/2 lower than those of the other two in the stop band, and shows the best noise density in the pass band. The sensitivity densities of two types of leapfrog filters are approximately equivalent, while that of the direct SFG simulation filter is much higher. However, the pass band response of the simplest configuration is not as good as those of the other two because of two parasitic zeros (at 708 kHz, -31.6 dB and 1.59 MHz, -20.55 dB) and a parasitic pole (at 4.57 MHz, 45.5 dB).
文摘A novel four-input three-output voltage-mode differential difference current conveyor (DDCC) based universal filter is presented. The circuit uses three DDCCs as active elements, two resistors and two capacitors as passive elements. The circuit along with its versatility enjoys the advantage of minimum number of passive elements employment. SPICE simulation results are given to confirm the theoretical analysis. The proposed circuit is a novel addition to the existing knowledge on the subject.
文摘This paper proposes an nth order (where n = 2,3, ,n) voltage mode active-C filter using n number of current controlled current conveyors (CCCIIs) and n number of equal valued grounded capacitors. The proposed topology can implement both band pass and low pass responses without alteration of any components. The filters offer the following important features: use of minimum number of current controlled current conveyors (CCCIIs) and passive components, no matching constraint, use of all grounded capacitors and absence of external resistor suitable for integration, cut off frequency can easily be electronically adjusted using AMS 0.35 μm CMOS technology. PSPICE simulation results of third order band pass and low pass responses are provided. The results are found to agree well with the theory.
文摘In this paper, an application of voltage differencing voltage transconductance amplifier (VDVTA) in the realization of voltage-mode (VM) multi-input single output (MISO) type biquad is presented. The proposed topology uses one VDVTA as an active element, two capacitors and a grounded resistor. The configuration realizes low pass (LP), high pass (HP), band pass (BP) and notch (BR) filters without the requirement of any matching condition. The natural frequency (w0) and bandwidth (BW) are independently controllable. The proposed circuit offers low active and passive sensitivities of w0. The operation of the proposed circuit has been verified through SPICE simulation with TSMC CMOS 0.18 μm process parameters.
文摘Two new current mode active-RC networks using the second generation current conveyer (CCII) devices are presented. The circuits provide high-Q bandpass (BP)/lowpass(LP) filter characteristics; the highpass(HP) response may also be obtained with suitable design. Current mode sine wave signal generation (Q→α) is possible by tuning a grounded resistor. With non-ideal CCIIs the design equations are slightly altered owing to CCII port current and voltage tracking errors (Ei,v).
文摘This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA). The proposed filter provides the following important and desirable features: (i) One can use only one CCDDCCTA and two capacitors;(ii) One can get low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) current responses from the same configuration without any alteration;(iii) Passive components are grounded, which ease the integrated circuit implementation;(iv) Responses are electronically tunable;and (v) Sensitivity is low. Moreover, the non-ideality analysis shows that the parasitic passive components can be compensated for the proposed circuit. The functionality of the design is verified through SPICE simulations using 0.25 μm CMOS TSMC technology process parameters. Simulation result agrees well with the theoretical analysis.
文摘The paper presents a new universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors. The offered structure has three inputs and one output and can realise all the five basic biquadratic filters: high-pass (HP), low-pass (LP), band-reject (BR), band-pass (BP) and all-pass (AP) from the same circuit topology. The proposed universal filter also provides following advantageous features, not available simultaneously in any UVC based universal biquadratic filter so far: (i) low active and passive sensitivities, (ii) independent control of natural frequency (ω0) and bandwidth (BW) and (iii) no requirement of any component matching condition and inversion of input signal(s) (as needed in most of the earlier reported structures). The workability of proposed structure has been presented by SPICE (Version 16.5) simulation using 0.18 μm TSMC technology.
基金Supported by the National Natural Science Foundation of China(61271113)
文摘A binary tree representation is designed in this paper for optimization of wave digital filter(WDF)implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array(FPGA)resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.
