An Analog Front End for Recording Neuronal Activity in Freely Behaving Small Animals

Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here, a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end (AFE),while a computer (Pentium III ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.

An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure （6 MSB 5 LSB） composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 #m 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 U/conversion-step.

A 14-bit 40-MHz analog front end for CCD application

A 14-bit,40-MHz analog front end（AFE） for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier（VGA） with nearly 42 dB gain range,a correlated double sampler（CDS） with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion（SNDR） is 70.3 dB,the effective number of bits is 11.39 bit.

An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) trans- ponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD) protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware

Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.

单对线以太网物理层模拟前端设计思考

单对线以太网是近年来新兴的以太网技术,随着汽车自动驾驶和工业物联网的高速发展,凭借上层应用扩展和底层布线上的绝对优势,正在大规模应用。单对线以太网物理层模拟前端技术是实现单对线以太网通信的关键基础技术。本文讲述了现有单对线以太网物理层模拟前端相关的标准,架构及相关模块设计技术,重点对发射器TX和接收器RX关键模块的现有实现技术及其优缺点进行了列举分析。发射器TX电流模结构易于实现高精度但功耗效率低,电压模结构精度略低但功耗效率更高;接收器RX的设计围绕模拟数字转换器(Analog-to-Digital Converter,ADC)展开,ADC决定着整个RX的性能、功耗、面积和复杂度,分段和重新装配(Segmentation And Reassembly,SAR)ADC是首选结构,应用上限不断提高。由此进一步明确了在高性能、低功耗、小面积的单对线以太网物理层模拟前端设计中的挑战。

基于反射式柔性探头及AFE4490的无线脉搏波监测系统

脉搏和血氧是人体重要的生理参数,能够反映生理和病理方面的相关信息。该系统设计了一款基于柔性反射式探头和集成模拟前端AFE4490的无线脉搏波监测系统,适用于监测人体额头部位的脉搏波和血氧水平。该系统主要由反射式柔性探头、集成模拟前端AFE4490、电源模块、主控MCU和Wi-Fi模块组成。采集到的脉搏波数据经过下位机处理后,无线传输至智能手机端,并在应用软件上实时显示当前的脉搏波形、脉率和血氧水平。经过相关测试和验证,该系统能够精确检测脉搏波信号,满足可穿戴设备的需求,并具有显著的市场应用潜力。

基于LabVIEW的模拟前端电压标定系统设计

电池管理系统中模拟前端的电压采集模块的精准采集对汽车预警起着关键性作用,同时目前电压采集模块手动及半自动标定过程中存在操作复杂、效率低和复用性差等问题,针对以上问题设计了一套对模拟前端中的电压采集模块进行标定的系统,通过LabVIEW上位机软件自动控制各仪器设备的方式,完成模拟前端电压采集模块的标定。通过实际测试,系统能够自动标定,实现操作简单、效率提升、高精度和复用性强等目标。

A review of automatic detection of epilepsy based on EEG signals

Epilepsy is a common neurological disorder that occurs at all ages.Epilepsy not only brings physical pain to patients,but also brings a huge burden to the lives of patients and their families.At present,epilepsy detection is still achieved through the observation of electroencephalography(EEG)by medical staff.However,this process takes a long time and consumes energy,which will create a huge workload to medical staff.Therefore,it is particularly important to realize the automatic detection of epilepsy.This paper introduces,in detail,the overall framework of EEG-based automatic epilepsy identification and the typical methods involved in each step.Aiming at the core modules,that is,signal acquisition analog front end(AFE),feature extraction and classifier selection,method summary and theoretical explanation are carried out.Finally,the future research directions in the field of automatic detection of epilepsy are prospected.

一种摆率可控的PD发射机模拟前端电路的设计

文章针对通用串行总线(universal serial bus,USB)电源传输协议(power delivery,PD)通信过程中的电磁干扰(electromagnetic interference,EMI)以及传统电路中电容不同带来的工艺偏差的影响,从电路层面对PD发射机模拟前端进行优化设计,提出一种摆率可控的PD发射机模拟前端电路。采用同一电流双路对称镜像进行单电容充放电结构,抑制了电容不同带来的工艺偏差的影响,并通过调节电流进行摆率控制,可有效抑制电磁干扰,输出级采用高增益两级运放组成的驱动器来提供强驱动能力。采用HHGRACE 0.35μm BCD工艺进行电路和版图设计,利用Spectre和Hspice软件进行仿真验证。仿真结果表明,设计指标满足USB PD协议标准的要求。

便携式心电采集设备设计与实现

针对心律不齐、心肌缺血、早搏等心脏疾病的相关人群,设计了一款便携式心电监测设备,用于疾病的早期发现和预防。首先对一款型号为RT1025的前端心电信号采集芯片进行了研究,并针对肌电噪声、50 Hz工频干扰等常见噪声开发了去噪声无限冲激响应滤波算法,最后完成了心电数据采集和通信的程序设计。该设备工作状态稳定,数据采集和控制简单,为便携式心电采集设备的设计提供了参考依据,对于预防和实时监测心血管方面的疾病具有重要意义。

基于FPGA的语音预处理系统

文中介绍了一种语音预处理系统的设计思路以及在FPGA平台下的实现方法。系统由模拟前端电路(Analog Front End,AFE)、高速Flash存储电路和PC端的数据处理模块构成。该系统主要功能是对语音信号实行预处理,通过AFE中的模拟回环功能获得预处理过的语音模拟信号,同时可向PC端发送未经处理的原始数据,并结合LMS自适应滤波算法可滤除杂波,得到较为纯净的语音数字信号。相比较其他语音处理方式,该系统既可将原始语音信号处理成低噪的数字信号,也可通过内部回环模式得到底噪且增益可放大的模拟信号。

一款AGV磁导航传感器的设计

在工业自动化的发展过程中,AGV(自动导引车辆)广泛投入使用,目前应用较广泛的导航方式之一是磁条导航,它具有对环境要求低、安装简单、易维护、成本低等优点。设计了一款AGV磁导航传感器,该传感器以ARM Cortex-M3为核心、RS232C线驱动和磁导航模拟前端设计硬件实验平台,实时采集磁导航信号,采集到的信号通过对数-双曲正切函数的鲁棒自适应滤波算法,减小AGV行驶过程中的偏差,在μC/OS Ⅲ微型操作系统进行任务循环调度,通过人机交互界面观测传感器实时状态,对AGV的运行轨迹进行修正。根据实验数据和仿真结果表明:使用该磁导航传感器的AGV行驶偏差较小,车身更加平稳。

A 410 μW, 70 dB SNR high performance analog front-end for portable audio application

This paper describes an analog front-end （AFE） intended for portable audio application, which operates at 1 V and consumes only 410 μW. The AFE consists of a 30 dB-gain programmable gain amplifier （PGA） and a 2nd-order 3-bit sigma-delta modulator. The PGA with single input and on-chip common-mode bias voltage shows good noise-reduction performance. The modulator makes use of data weighted averaging to reduce the linearity requirements of the digital-to-analog converter in the feedback loop. The AFE is implemented in the SMIC 0.13μm 1PSM CMOS process. The measurement results show that in a 1 V power supply, at 200 mVp-p, between 100 Hz and 20 kHz, the maximal signal-to-noise ratio is 70 dB, and the total power is 410 μW.

A CMOS analog front-end chip for amperometric electrochemical sensors

This paper reports a complimentary metal-oxide-semiconductor （CMOS） analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I^2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter （∑-△ ADC） are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm^2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L.

Design of an analog front-end for ambulatory biopotential measurement systems

A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms （0.48-2000 Hz）. The chip is fabricated via a SMIC 0.18μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

CCD成像系统中模拟前端设计

CCD成像系统中模拟前端对系统信噪比起决定性作用。为了提高成像系统的信噪比,需要对模拟前端以及其PCB布局布线进行合理的设计。在深入分析模拟前端中各部分功能的基础上,针对目前模拟前端一般采用专用CCD视频信号处理器来实现的方案,建立了CCD视频信号处理器这个模拟数字混合器件芯片内部的电源及接地模型,并根据该模型对PCB布局布线进行了分析和设计。工程实践结果表明,在像素时钟为6 MHz时,系统的信噪比可以达到54dB。

RFID标签芯片的最新研究进展

射频识别(RFID)系统是一种具有广泛应用前景的自动识别系统。近年来,射频识别技术以快速增长趋势在供应链、门禁、公交系统、行李跟踪等领域获得了广泛的应用。文章详细论述了不同频段RFID标签芯片的最新研究进展,对标签芯片的核心模块射频模拟前端、数字控制器、存储器的研究及发展趋势进行了分析。最后,讨论了标签芯片的发展方向。

动力锂电池组充放电智能管理系统

提出了一种全新的动力锂电池组充放电智能管理系统,以ISL9216、ISL9217为模拟前端(AFE),ATmega32为控制芯片,MAX1033为辅助锂电池电压采集IC,DS18B20为单节锂电池温度传感器,成功地实现了一个14节锂电池串联动力锂电池组的充放电过电流保护和放电时短路电流保护,充放电循环次数记录,单节锂电池电压监测,电池组温度监测以及高达200mA平衡电流的快速电量平衡等功能,具有体积小,成本低,精度高,反应快,电路简洁等优点。

高频RFID读写器射频模拟前端的实现

射频识别(RFID)系统主要由RFID读写器和RFID电子标签两部分组成。给出了高频(13.56MHz)RFID系统中读写器射频模拟前端的电路设计,符合ISO/IEC14443typeA/typeB,ISO/IEC15693和ISO/IEC18000-3中任一个标准的读写器芯片设计均可采用,设计工艺采用了中芯国际0.35μm2P3M混合CMOS技术,并给出了Cadence环境下的仿真结果。