Surface integral analogy approaches for predicting noise from 3D high-lift low-noise wings

Three surface integral approaches of the acoustic analogies are studied to predict the noise from three concep- tual configurations of three-dimensional high-lift low-noise wings. The approaches refer to the Kirchhoff method, the Ffowcs Williams and Hawkings （FW-H） method of the permeable integral surface and the Curle method that is known as a special case of the FW-H method. The first two approaches are used to compute the noise generated by the core flow region where the energetic structures exist. The last approach is adopted to predict the noise specially from the pressure perturbation on the wall. A new way to con- struct the integral surface that encloses the core region is proposed for the first two methods. Considering the local properties of the flow around the complex object-the actual wing with high-lift devices-the integral surface based on the vorticity is constructed to follow the flow structures. The surface location is discussed for the Kirchhoff method and the FW-H method because a common surface is used for them. The noise from the core flow region is studied on the basis of the dependent integral quantities, which are indicated by the Kirchhoff formulation and by the FW-H formulation. The role of each wall component on noise contribution is analyzed using the Curle formulation. Effects of the volume integral terms of Lighthill＇s stress tensors on the noise pre-diction are then evaluated by comparing the results of the Curle method with the other two methods.

Hierarchical Symbolic Analysis of Large Analog Circuits with Totally Coded Method

Symbolic analysis has many applications in the design of analog circuits. Existing approaches rely on two forms of symbolic-expression representation: expanded sum-of-product form and arbitrarily nested form. Expanded form suffers the problem that the number of product terms grows exponentially with the size of a circuit. Nested form is neither canonical nor amenable to symbolic manipulation. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. This algorithm, called totally coded method (TCM), consists of representing the symbolic determinant of a circuit matrix by code series and performing symbolic analysis by code manipulation. We describe an efficient code-ordering heuristic and prove that it is optimum for ladder-structured circuits. For practical analog circuits, TCM not only covers all advantages of the algorithm via determinant decision diagrams (DDD) but is more simple and efficient than DDD method.

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

Totally Coded Algorithm for Switched-Current Network Analysis in Frequency Domain

Based on mirror-blocks, a totally coded algorithm （TCA） for switched-current （SI） network analysis in frequency domain is presented. The algorithm is simple, available, and suitable for any swltched-current networks. A basis of analysis and design for switched-current networks via this algorithm is provided.

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35μm CMOS is presented. The circuit consists of two variable gain amplifiers（VGA） in cascade and a Gm-C elliptic low-pass filter（LPF）. The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide -10 to ＋40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.

Analog Module Placement Design Using Genetic Algorithm

This paper presents a novel genetic algorithm for analog module placement based on a generalization of the two-dimensional bin packing problem. The genetic encoding and operators assure that all problem constraints are always satisfied. Thus the potential problems of adding penalty terms to the cost function are eliminated so that the search configuration space is drastically decreased. The dedicated cost function is based on the special requirements of analog integrated circuits. A fractional factorial experiment was conducted using an orthogonal array to study the algorithm parameters. A meta-GA was applied to determine the optimal parameter values. The algorithm was tested with several local benchmark circuits. The experimental results show that the algorithm has better performance than the simulated annealing approach with satisfactory results comparable to manual placement. This study demonstrates the effectiveness of the genetic algorithm in the analog module placement problem. The algorithm has been successfully used in a layout synthesis tool.

A multi-channel analog IC for in vitro neural recording

Recent work in the field ofneurophysiology has demonstrated that, by observing the firing characteristic of action potentials （AP） and the exchange pattern of signals between neurons, it is possible to reveal the nature of ＂memory＂ and ＂thinking＂ and help humans to understand how the brain works. To address these needs, we developed a prototype fully integrated circuit （IC） with micro-electrode array （MEA） for neural recording. In this scheme, the microelectrode array is composed by 64 detection electrodes and 2 reference electrodes. The proposed IC consists of 8 recording channels with an area of 5 x 5 mm2. Each channel can operate independently to process the neural signal by amplifying, filtering, etc. The chip is fabricated in 0.5-#m CMOS technology. The simulated and measured results show the system provides an effective device for recording feeble signal such as neural signals.

Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.

A 3V 5.88mW 13b 400kHz Sigma-Delta Modulator with 84dB Dynamic Range

This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

DC Gain Analysis of Scaled CMOS Op Amp in Sub-100 nm Technology Nodes:A Research Based on Channel Length Modulation Effect

Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.