The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network con...The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.展开更多
为解决双向励磁涡流检测传感器的信号解调问题,设计了适用于低频范围的正交解调电路(包括移相器、模拟乘法器以及低通滤波器),并对电路各模块的特性进行了测试.通过在移相器中设置滑动变阻器调节两级运放的输入、输出阻抗,可以实现对10~...为解决双向励磁涡流检测传感器的信号解调问题,设计了适用于低频范围的正交解调电路(包括移相器、模拟乘法器以及低通滤波器),并对电路各模块的特性进行了测试.通过在移相器中设置滑动变阻器调节两级运放的输入、输出阻抗,可以实现对10~30 k Hz内正弦信号的90°相移,测试了乘法器在工作频段内的直流偏置特性.将解调电路与双向励磁涡流检测传感器应用于钢块不同深度缺陷的检.结果表明:偏置电压基本不随工作频率而波动,进行差值补偿后,计算与电路输出结果的互相关系数为0.955 1,整体解调电路对信号解调的幅值误差小于13%,相位解调误差小于8%.可以检测出45号钢中深7 mm的槽型缺陷,且随着缺陷深度的增加,幅值和相位均呈增长趋势.展开更多
A new reflection-type wideband 360° monolithic-microwave integrated-circuit （MMIC） analog phase shifter at the Ka-band is proposed. The phase shifter is designed based on the principle of vector synthesis. Thre...A new reflection-type wideband 360° monolithic-microwave integrated-circuit （MMIC） analog phase shifter at the Ka-band is proposed. The phase shifter is designed based on the principle of vector synthesis. Three Lange couplers are employed in the phase shifter, which is fabricated by the standard 0.25μzm GaAs process. We use four 4 × 40μm GaAs HEMTs as the reflection loads. A microstrip line in parallel with the device is used as an inductance to counteract the parasitic capacitance of the device so that the reflection load performs like a pure resistance and the insertion loss can be decreased. In this phase shifter, a folded Lange coupler is utilized to reduce the size of the chip. The size of the proposed MMIC phase shifter is only 2.0 × 1.2 mm2. The measurement results show that the insertion loss is 5.0 4- 0.8 dB and a 360°continuously tunable range across 27-32 GHz is obtained with miniscule DC power consumption.展开更多
本报告论述了软件化雷达(Software Defined Radar,SDR)的内涵、基本特点和总体架构,并分析了软件化雷达的中移相器和变频器的数字化的发展趋势,论述了SDR对ADC动态范围、量化精度以及采样速度的要求,分析了低成本有源相控阵雷达架构在未...本报告论述了软件化雷达(Software Defined Radar,SDR)的内涵、基本特点和总体架构,并分析了软件化雷达的中移相器和变频器的数字化的发展趋势,论述了SDR对ADC动态范围、量化精度以及采样速度的要求,分析了低成本有源相控阵雷达架构在未来SDR架构中的应用前景。展开更多
A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design ...A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.展开更多
基金supported by Iran Telecommunication Research Center under Grant No. 4222/500
文摘The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.
文摘为解决双向励磁涡流检测传感器的信号解调问题,设计了适用于低频范围的正交解调电路(包括移相器、模拟乘法器以及低通滤波器),并对电路各模块的特性进行了测试.通过在移相器中设置滑动变阻器调节两级运放的输入、输出阻抗,可以实现对10~30 k Hz内正弦信号的90°相移,测试了乘法器在工作频段内的直流偏置特性.将解调电路与双向励磁涡流检测传感器应用于钢块不同深度缺陷的检.结果表明:偏置电压基本不随工作频率而波动,进行差值补偿后,计算与电路输出结果的互相关系数为0.955 1,整体解调电路对信号解调的幅值误差小于13%,相位解调误差小于8%.可以检测出45号钢中深7 mm的槽型缺陷,且随着缺陷深度的增加,幅值和相位均呈增长趋势.
基金Project supported by the National Natural Science Foundation of China(No.61334002)the Opening Project of Science and Technologyon Reliability Physics and Application Technology of Electronic Component Laboratory(No.ZHD201206)the Program for New Century Excellent Talents in University(No.NCET-12-0915)
文摘A new reflection-type wideband 360° monolithic-microwave integrated-circuit （MMIC） analog phase shifter at the Ka-band is proposed. The phase shifter is designed based on the principle of vector synthesis. Three Lange couplers are employed in the phase shifter, which is fabricated by the standard 0.25μzm GaAs process. We use four 4 × 40μm GaAs HEMTs as the reflection loads. A microstrip line in parallel with the device is used as an inductance to counteract the parasitic capacitance of the device so that the reflection load performs like a pure resistance and the insertion loss can be decreased. In this phase shifter, a folded Lange coupler is utilized to reduce the size of the chip. The size of the proposed MMIC phase shifter is only 2.0 × 1.2 mm2. The measurement results show that the insertion loss is 5.0 4- 0.8 dB and a 360°continuously tunable range across 27-32 GHz is obtained with miniscule DC power consumption.
基金supported by the National Natural Science Foundation of China(Nos.60676009,60725415,60776034,60803038)the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260).
文摘A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.
