Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

Design of Digital to Analog Converters with Arbitrary Radix

There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Performance Evaluation of Wavelength Division Multiplexing Photonic Analogue-to-Digital Converters for High-Resolution Radar Systems

The performance of the wavelength division multiplexing (WDM) photonic analogue-to-digital converter (ADC) used for digitization of high-resolution radar systems is evaluated numerically by using the peak signal-to-noise ratio (SNR) metric. Two different WDM photonic ADC architectures are considered for the digitization of radar signals with 5 GHz of bandwidth (spatial resolution of 3 cm), in order to provide a comprehensive study of the compromises present when deploying radar signals with high-resolution: 1) a four-channel architecture with each channel employing an ADC with 5 GSamples/s, and 2) an eight-channel architecture with each channel employing an ADC with 2.5 GSamples/s. For peak powers of the pulsed source between 10 and 20 dBm and a distance between the radar antenna and the sensing object of 2.4 meters, peak SNR levels between 29 and 39 dB are achieved with the eight-channel architecture, which shows higher peak SNR levels when compared with the four-channel architecture. For the eight-channel architecture and for the same peak powers of the pulsed source, peak SNR levels between 11 and 16 dB are obtained when the distance increases to 13.5 meters. With this evaluation using the peak SNR, it is possible to assess the performance limits when choosing a specific radar range, while keeping the same resolution.

An Adaptive Control Strategy for Energy Storage Interface Converter Based on Analogous Virtual Synchronous Generator

In the DC microgrid,the lack of inertia and damping in power electronic converters results in poor stability of DC bus voltage and low inertia of the DC microgrid during fluctuations in load and photovoltaic power.To address this issue,the application of a virtual synchronous generator(VSG)in grid-connected inverters control is referenced and proposes a control strategy called the analogous virtual synchronous generator(AVSG)control strategy for the interface DC/DC converter of the battery in the microgrid.Besides,a flexible parameter adaptive control method is introduced to further enhance the inertial behavior of the AVSG control.Firstly,a theoretical analysis is conducted on the various components of the DC microgrid,the structure of analogous virtual synchronous generator,and the control structure’s main parameters related to the DC microgrid’s inertial behavior.Secondly,the voltage change rate tracking coefficient is introduced to adjust the change of the virtual capacitance and damping coefficient flexibility,which further strengthens the inertia trend of the DC microgrid.Additionally,a small-signal modeling approach is used to analyze the approximate range of the AVSG’s main parameters ensuring system stability.Finally,conduct a simulation analysis by building the model of the DC microgrid system with photovoltaic(PV)and battery energy storage(BES)in MATLAB/Simulink.Simulation results from different scenarios have verified that the AVSG control introduces fixed inertia and damping into the droop control of the battery,resulting in a certain level of inertia enhancement.Furthermore,the additional adaptive control strategy built upon the AVSG control provides better and flexible inertial support for the DC microgrid,further enhances the stability of the DC bus voltage,and has a more positive impact on the battery performance.

Investigation on Analog and Digital Modulations Recognition Using Machine Learning Algorithms

In the field of radiocommunication, modulation type identification is one of the most important characteristics in signal processing. This study aims to implement a modulation recognition system on two approaches to machine learning techniques, the K-Nearest Neighbors (KNN) and Artificial Neural Networks (ANN). From a statistical and spectral analysis of signals, nine key differentiation features are extracted and used as input vectors for each trained model. The feature extraction is performed by using the Hilbert transform, the forward and inverse Fourier transforms. The experiments with the AMC Master dataset classify ten (10) types of analog and digital modulations. AM_DSB_FC, AM_DSB_SC, AM_USB, AM_LSB, FM, MPSK, 2PSK, MASK, 2ASK, MQAM are put forward in this article. For the simulation of the chosen model, signals are polluted by the Additive White Gaussian Noise (AWGN). The simulation results show that the best identification rate is the MLP neuronal method with 90.5% of accuracy after 10 dB signal-to-noise ratio value, with a shift of more than 15% from the k-nearest neighbors’ algorithm.

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.

Design of low-power high-frequency digital controlled DC-DC switching power converter

This paper models a low-power high-frequency digitally controlled synchronous rectifier （SR） OUCK converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems such as quantization resolution of digital pulse-width modulation （DPWM） and steady-state limit cycles of digital control switching model power supply （SMPS） are discussed, with corresponding solutions presented. Simulation of a digital control synchronous buck is performed with a fixed-point algorithm. The results show that the described approach enables high-speed dynamic performance.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Digital Control Technologies for DC/DC Switching Converters

An overview of recent advances in digital control of low-to medium-power DC/DC switching converters is presented.Traditionally,analog electronics methods have dominated in controlling such DC/DC converters.However,with the steadily decreasing cost of ICs,the feasibility of digitally controlled DC/DC switching converters has increased sig-nificantly.This paper outlines a sample of digital solutions for DC/DC switching converters to enhance the performance of DC/DC switching converters.Furthermore,latest research activities pertaining to applications for steady-state and dy-namic performance improvement,such as efficiency optimization,controller auto tuning,and capacitor charge balance control,is discussed.These applications demonstrate the significant advantages and potentials of digital control.

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.

PULSE SHRINKING TIME-TO-DIGITAL CONVERTER FOR UWB APPLICATION

A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.

Energy-Efficient Large-Scale Antenna Systems with Hybrid Digital-Analog Beamforming Structure

A largescale antenna system （LSAS） with digital beamforming is expected to significantly increase energy efficiency （EE） and spectral efficiency （SE） in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digitalanalog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N ＆#215; M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EESE curve, and show that the logscale EE scales linearly with SE along a slope of lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal （N, M） combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.

A Design of High-precision High-Voltage Fiber-Optic Analog Signal Isolation Converter

This paper introduces a design of high-precision high-voltage fiber-optic analog sig-nal isolation converter based on the technology of Voltage-to-Frequency (V/F) and Frequency-to-Voltage (F/V) conversion. It describes the principle, system configuration and hardware design.