Flexural wave band-gaps in phononic metamaterial beam with hybrid shunting circuits

Periodic arrays of hybrid-shunted piezoelectric patches are used to control the band-gaps of phononic metamaterial beams. Passive resistive-inductive （RL） shunting circuits can produce a narrow resonant band-gap （RG）, and active negative capacitive （NC） shunting circuits can broaden the Bragg band-gaps （BGs）. In this article, active NC shunting circuits and passive resonant RL shunting circuits are connected to the same piezoelectric patches in parallel, which are usually called hybrid shunting circuits, to control the location and the extent of the band-gaps. A super-wide coupled band-gap is generated when the coupling between RG and the BG occurs. The attenuation constant of the infinite periodic structure is predicted by the transfer matrix method, which is compared with the vibration transmittance of a finite periodic structure calculated by the finite element method. Numerical results show that the hybrid-shunting circuits can make the band-gaps wider by appropriately selecting the inductances, negative capacitances, and resistances.

Hybrid material integration in silicon photonic integrated circuits

Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.

Total ionizing dose effect modeling method for CMOS digital-integrated circuit

Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID effects in complementary metaloxide semiconductor(CMOS)digital ICs based on the input/output buffer information specification(IBIS)was proposed.The digital IC was first divided into three parts based on its internal structure:the input buffer,output buffer,and functional area.Each of these three parts was separately modeled.Using the IBIS model,the transistor V-I characteristic curves of the buffers were processed,and the physical parameters were extracted and modeled using VHDL-AMS.In the functional area,logic functions were modeled in VHDL according to the data sheet.A golden digital IC model was developed by combining the input buffer,output buffer,and functional area models.Furthermore,the golden ratio was reconstructed based on TID experimental data,enabling the assessment of TID effects on the threshold voltage,carrier mobility,and time series of the digital IC.TID experiments were conducted using a CMOS non-inverting multiplexer,NC7SZ157,and the results were compared with the simulation results,which showed that the relative errors were less than 2%at each dose point.This confirms the practicality and accuracy of the proposed modeling method.The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID,which has potential applications in the design of radiation-hardening tolerance in digital ICs.

Analysis of learnability of a novel hybrid quantum-classical convolutional neural network in image classification

We design a new hybrid quantum-classical convolutional neural network(HQCCNN)model based on parameter quantum circuits.In this model,we use parameterized quantum circuits(PQCs)to redesign the convolutional layer in classical convolutional neural networks,forming a new quantum convolutional layer to achieve unitary transformation of quantum states,enabling the model to more accurately extract hidden information from images.At the same time,we combine the classical fully connected layer with PQCs to form a new hybrid quantum-classical fully connected layer to further improve the accuracy of classification.Finally,we use the MNIST dataset to test the potential of the HQCCNN.The results indicate that the HQCCNN has good performance in solving classification problems.In binary classification tasks,the classification accuracy of numbers 5 and 7 is as high as 99.71%.In multivariate classification,the accuracy rate also reaches 98.51%.Finally,we compare the performance of the HQCCNN with other models and find that the HQCCNN has better classification performance and convergence speed.

A Hybrid GA-SQP Algorithm for Analog Circuits Sizing

This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.

The Voltage Distribution Characteristics of a Hybrid Circuit Breaker During High Current Interruption

Hybrid circuit breaker （HCB） technology based on a vacuum interrupter and a SF6 interrupter in series has become a new research direction because of the low-carbon requirements for high voltage switches. The vacuum interrupter has an excellent ability to deal with the steep rising part of the transient recovery voltage （TRV）, while the SF6 interrupter can withstand the peak part of the voltage easily. An HCB can take advantage of the interrupters in the current interruption process. In this study, an HCB model based on the vacuum ion diffusion equations, ion density equation, and modified Cassie-Mayr arc equation is explored. A simulation platform is constructed by using a set of software called the alternative transient program （ATP）. An HCB prototype is also designed, and the short circuit current is interrupted by the HCB under different action sequences of contacts. The voltage distribution of the HCB is analyzed through simulations and tests. The results demonstrate that if the vacuum interrupter withstands the initial TRV and interrupts the post-arc current first, then the recovery speed of the dielectric strength of the SF6 interrupter will be fast. The voltage distribution between two interrupters is determined by their post-arc resistance, which happens after current-zero, and subsequently, it is determined by the capacitive impedance after the post-arc current decays to zero.

Mechanism of hybrid-magnetic-circuit multi-couple motor

Discusses the interval between laminations in a permanent magnet inductor motor which makes the air gap magnetic field produced by the permanent magnet very uneven in the axial direction, and limits the performance of a motor. Proposes a hybrid magnetic circuit multi couple motor to compensate for the uneven air gap magnetic field, thereby improving the performance of a motor.

Key stress extraction and equivalent test method for hybrid DC circuit breaker

Firstly, relevant stress properties of millisecond level breaking process and microsecond level commutation process of hybrid HVDC circuit breaker are studied in detail on the basis of the analysis for the application environment and topological structure and operating principles of hybrid circuit breakers, and key stress parameters in transient state process of two time dimensions are extracted. The established digital simulation circuit for PSCAD/EMTDC device-level operation of the circuit breaker has verified the stress properties of millisecond level breaking process and microsecond level commutation process. Then, equivalent test method, circuits and parameters based on LC power supply are proposed on the basis of stress extraction. Finally, the results of implemented breaking tests for complete 200 kV circuit breaker, 100 kV and 50 kV circuit breaker units, as well as single power electronic module have verified the accuracy of the simulation circuit and mathematical analysis. The result of this paper can be a guide to electrical structure and test system design of hybrid HVDC circuit breaker.

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

A Fault Current Limiting Hybrid DC Circuit Breaker

Due to the low impedance characteristic of the high voltage direct current(HVDC)grid,the fault current rises extremely fast after a DC-side fault occurs,and this phenomenon seriously endangers the safety of the HVDC grid.In order to suppress the rising speed of the fault current and reduce the current interruption requirements of the main breaker(MB),a fault current limiting hybrid DC circuit breaker(FCL-HCB)has been proposed in this paper,and it has the capability of bidirectional fault current limiting and fault current interruption.After the occurrence of the overcurrent in the HVDC grid,the current limiting circuit(CLC)of FCL-HCB is put into operation immediately,and whether the protected line is cut off or resumed to normal operation is decided according to the fault detection result.Compared with the traditional hybrid DC circuit breaker(HCB),the required number of semiconductor switches and the peak value of fault current after fault occurs are greatly reduced by adopting the proposed device.Extensive simulations also verify the effectiveness of the proposed FCL-HCB.

Some Tools to Model Ground or Supply Bounces Induced in and out of Heterogeneous Integrated Circuits

Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.

具备自适应重合闸能力的多端口混合式直流断路器

为解决柔性直流电网中混合式直流断路器成本高以及盲目重合闸的问题,提出了一种具备自适应重合闸能力的多端口混合式直流断路器。所提断路器能够在能量耗散期间旁路故障线路中的限流电抗器,配合电容充电回路的导通,将本应经避雷器耗散的限流电抗器能量转移到电容中,从而有效减少了故障隔离时间与避雷器能量耗散压力,并为故障性质的判别提供了能量支持。同时,该断路器通过共享主断路器的方式实现故障隔离,结合避雷器泄能需求的下降,大大降低了断路器的制造成本,在经济性方面优势明显。此外,该断路器利用故障识别电流与电容电压在永久性故障与瞬时性故障下的幅值差异来识别故障性质,实现了自适应重合闸,操作简单且易于控制。最后,利用PSCAD/EMTDC在三端MMC柔性直流系统环境下对所提方案的有效性进行了仿真验证,并通过与其他方案的对比分析,证明了所提方案的优越性。

基于电容自然充电换相的混合式直流断路器设计与仿真

以晶闸管作为主断器件是降低混合式直流断路器造价和技术难度的手段之一,电容电压是此类直流断路器能够顺利开断直流故障的关键影响因素。现有结构中电容大多为预充电型,但预充电方式和电容电压的维持较为复杂。因此,该文提出一种基于电容自然充电换相的混合式直流断路器,利用母线电压与预充电电容的电压差值实现电容的预充电和电容电压的自动维持,从而保证断路器的开断能力。此外该断路器还具备二次开断能力,可以满足极短时间内重复开断的需求。针对所提断路器的工作过程和元器件参数进行了详细的理论推导,基于PSCAD/EMTDC建立单端等效和四端柔性直流电网模型验证了所提结构的适用性。最后与其他方案进行比较,结果表明,所提方案在开断速度、电容预充电方式和二次开断方面具备一定优势。

一种基于电容主动钳位式混合式直流断路器

混合式直流断路器兼具机械式直流断路器的静态特性与固态直流断路器的动态特性,具有较快的开断速度和较低的通态损耗,是应用于中高压直流输配电系统的优选技术方案。然而,基于模块级联的混合式直流断路器存在投资成本较高、避雷器吸能较高、不具备故障性质判别能力等问题,限制了断路器的工程化应用。该文在现有结构的基础上进行一定的改进,提出一种基于电容主动钳位式混合式直流断路器。主要利用电容电压钳位换流站侧电压,避免了换流站电压迅速跌落的同时降低了换流站侧的故障电流峰值。此外,电容电压还可作为线路故障和重合闸时的辅助判据。针对所提结构进行了详细的理论推导和分析,在PSCAD/EMTDC中建立四端直流环网对所提结构进行验证,并与原有方案进行对比。仿真结果证明所提结构可行且相对原有方案具备一定优势。

固态断路器多IGBT串联混合均压电路设计

固态断路器需多IGBT串联切断短路故障电流,针对多IGBT存在电压分配不均、局部电压过高、损耗大等问题,提出一种混合式均压控制电路拓扑结构。分析固态断路器多IGBT均压影响因素,研究均压拓扑性能。优化缓冲电路结构,改进充放电型缓冲电路,减小损耗;引入双阈值钳位控制电路,改善IGBT过电压;提出被动均压与辅助反馈主动均压结合的混合均压控制策略,加快响应速度,实现均压动态自适应调节。制作样机,进行固态断路器设计拓扑和控制的仿真及实验验证,结果表明:混合式均压控制电路可减小IGBT电路超调量,具备更强的抑制过电压能力,提升响应速度。

一种双电容换流型混合式直流断路器

混合式直流断路器可以快速、准确隔离线路故障,在直流电网故障清除难题中发挥重要作用。为解决直流断路器开断能力要求高、限流能力弱、制造成本大、故障隔离速度慢等问题,提出一种双电容换流型混合式直流断路器(Double capacitor commutated hybrid DC circuit breaker,D-C-DCCB)拓扑。构建断路器时,巧妙利用自充电通路实现电容预充电及反向充电后电容能量的耗散。通过电容反向充电与阻感限流支路降低故障电流上升速率及峰值,利用限流电阻与二极管组实现限流电感,完成限流工作后被短路及储存能量耗散,加快故障隔离速度的同时,有效减少了避雷器吸收能量。对所提断路器的拓扑结构及工作原理进行分析及推导,在PSCAD/EMTDC中对所提断路器拓扑进行了四端直流电网仿真验证,与现有的直流电网故障清除拓扑在性能及经济性方面进行了对比,证明了所提断路器具有性能好、经济性高的优点。

混合式直流断路器状态感知技术与智慧框架体系探讨

直流断路器是柔性直流输电工程中故障清除和隔离的关键设备,当前的热点集中在新型拓扑结构、直流开断特性和新型电力电子器件等功能方面的研究,对其全状态的智能感知和状态评估方面研究较少。该文以混合式直流断路器为研究对象,全面梳理了需要重点监测的状态量,归纳了混合式直流断路器中快速机械开关、压接式绝缘栅双极性晶体管(insulated gate bipolar transistor,IGBT)、避雷器、快速机构动作电容和隔离供能单元等关键组件状态量的感知方法。基于现有研究,提出了智慧型直流断路器的框架体系。分析了所提框架体系中智能感知层、信息通信层、数据融合层和智能应用层的实现思路,为实现直流断路器的智能化和模块化提供一定参考依据。

“电路原理”混合式智慧教学的探索与实践

“电路原理”混合式智慧教学,以学生为中心,在优化设计教学内容、系统建设教学资源的基础上,将智慧教学平台和群聊工具引入课程,构建“课前预习—课堂学习—课后评价及反馈”知识点闭环教学系统,通过线上学习与线下教学混合、课内学习与课外自学混合、群聊工具与课程教学混合、理论学习与工程应用混合,在实现教与学充分融合的同时,促进学生自主学习能力,有效提高课程的教学质量。

一种可选择中断的混合式直流断路器拓扑

传统的混合式直流断路器应对瞬时性故障时必须先切断故障电流,再进行重合闸,会造成短暂性的电能供应中断。对此,提出一种适用于中压直流的可选择中断混合式直流断路器拓扑。该断路器可根据不同的故障类型选择运行方式,在与主导通支路串联的桥式结构中增加电容和限流电感抑制故障的电流上升,并储存能量,通过释能电阻对能量进行释放。对所提出的拓扑进行工作过程和理论分析。在单端直流等效系统中进行仿真验证,该结构在应对永久性短路故障时,可在9 ms内切除故障;应对瞬时性故障时,可使系统在不中断电流的情况下恢复正常运行,并释放故障时产生的能量。仿真结果验证了该拓扑的优越性。

真空与气体一体化串联机械开关及其直流快速转移应用

为提升中压混合式直流断路器的自然换流性能,该文提出一种真空与气体一体化串联机械开关,分析真空与气体一体化串联用于电流转移性能的工作原理。并基于此设计了双超程联动的真空与气体一体化串联开关实验样机,研究了气体类型、气压、触头结构、触头材料等参数对电弧电压特性的影响规律,确定了W70Cu桥式两触点结构,采用H2和N2体积比为2:3、气压为0.3 MPa的氢氮混合气体,弧压可由20 V提升到120 V,电流转移时间由1 900μs缩短至300μs。同时测试了静态瞬态开断电压(TIV)分布特性,真空间隙承担主要电压(55%),串联整机耐压水平为20 kV。验证了真空与气体一体化串联开关应用于中压混合式直流断路器的可行性和有效性。