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A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter
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作者 Qinghong Li Xianguo Cao +2 位作者 Liangbin Wang Zechu He Weiming Liu 《Open Journal of Applied Sciences》 2023年第10期1778-1786,共9页
With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co... With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB. 展开更多
关键词 Successive Approximation analog-to-digital converter SEGMENTED Capacitor Array
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Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example 被引量:1
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作者 Sheng-Gang Dong Xiao-Yang Wang +2 位作者 Hua Fan Jun-Feng Gao Qiang Li 《Journal of Electronic Science and Technology》 CAS 2013年第4期372-381,共10页
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. A... This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW. 展开更多
关键词 analog-to-digital converter asynchro-nous CLOCK review successive-approximation registeranalog-to-digital converters.
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Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters
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作者 王沛 龙善丽 吴建辉 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第9期1369-1374,共6页
Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAAD... Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave. 展开更多
关键词 analog-to-digital converter successive approximation self-calibration techniques
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Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions 被引量:1
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作者 李兴冀 刘超铭 +2 位作者 孙中亮 肖立伊 何世禹 《Chinese Physics B》 SCIE EI CAS CSCD 2013年第9期629-633,共5页
The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are inv... The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux. 展开更多
关键词 analog-to-digital converters enhanced low dose rate sensitivities (ELDRS) gamma ray and protonirradiation lower/high-dose rate
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Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing
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作者 王晓东 孙雨南 +1 位作者 伍剑 崔芳 《Journal of Beijing Institute of Technology》 EI CAS 2003年第S1期58-61,共4页
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital c... A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible. 展开更多
关键词 OADC(optical analog-to-digital converter) electrooptic sampling OTDM(optical time division multiplexing)
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A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch
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作者 李丹 戎蒙恬 毛军发 《Journal of Shanghai Jiaotong university(Science)》 EI 2007年第4期497-500,共4页
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa... A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs. 展开更多
关键词 charge TEMPORARY storage technique (CTST) residual voltage CAPACITOR MISMATCH PIPELINED analog-to-digital converter (ADC)
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A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter
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作者 Ling Du Ning Ning +2 位作者 Shuangyi Wu Qi Yu Yang Liu 《Journal of Computer and Communications》 2013年第6期30-36,共7页
A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC ... A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB. 展开更多
关键词 analog-to-digital CONVERSION CAPACITOR MISMATCH DIGITAL BACKGROUND Calibration SAR ADC
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A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology 被引量:4
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作者 余金山 张瑞涛 +5 位作者 张正平 王永禄 朱璨 张磊 俞宙 韩勇 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第1期108-115,共8页
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3... A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input. 展开更多
关键词 ultra high-speed wide-bandwidth FOLDING interpolating analog-to-digital converter
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Switching response of dual-output Mach–Zehnder modulator in channel-interleaved photonic analog-to-digital converter 被引量:5
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作者 Lei Yu Weiwen Zou +2 位作者 Guang Yang Xinwan Li Jianping Chen 《Chinese Optics Letters》 SCIE EI CAS CSCD 2018年第12期16-19,共4页
This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A fig... This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced. 展开更多
关键词 Zehnder modulator in channel-interleaved photonic analog-to-digital converter Switching response of dual-output Mach MZM
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A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control 被引量:3
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作者 Zongguang Yu Xiaobo Su +4 位作者 Zhenhai Chen Jiaxuan Zou Jinghe Wei Hong Zhang Yan Xue 《Tsinghua Science and Technology》 SCIE EI CAS CSCD 2018年第1期87-94,共8页
A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the prec... A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range (SFDR) of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2. 展开更多
关键词 pipelined analog-to-digital converter charge domain low power feed-forward control
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Wideband signal detection based on high-speed photonic analog-to-digital converter 被引量:3
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作者 Guang Yang Weiwen Zou +1 位作者 Ye Yuan Jianping Chen 《Chinese Optics Letters》 SCIE EI CAS CSCD 2018年第3期6-10,共5页
This Letter demonstrates the effectiveness of a high-speed high-resolution photonic analog-to-digital converter (PADC) for wideband signal detection. The PADC system is seeded by a high-speed actively mode locked la... This Letter demonstrates the effectiveness of a high-speed high-resolution photonic analog-to-digital converter (PADC) for wideband signal detection. The PADC system is seeded by a high-speed actively mode locked laser, and the sampling rate is multiplied via a time-wavelength interleaving scheme. According to the laboratory test, an X-band linear frequency modulation signal is detected and digitized by the PADC system. The channel mismatch effect in wideband signal detection is compensated via an algorithm based on a short-time Fourier transform. Consequently, the signal-to-distortion ratio (SDR) of the wideband signal detection is enhanced to the comparable SDR of the single-tone signal detection. 展开更多
关键词 SDR Wideband signal detection based on high-speed photonic analog-to-digital converter LFM
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A Novel All-Optical Analog-to-Digital Converter
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作者 Xiaobo Hou Afshin Daryoush Warren Rosen 《光学学报》 EI CAS CSCD 北大核心 2003年第S1期603-604,共2页
An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of ... An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures. 展开更多
关键词 GHZ in as LINE HIGH A Novel All-Optical analog-to-digital converter ADC been of
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A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch
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作者 景鑫 庄奕琪 +4 位作者 汤华莲 戴力 杜永乾 张丽 段宏波 《Journal of Semiconductors》 EI CAS CSCD 2014年第2期102-111,共10页
Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter(ADC)implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire inpu... Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter(ADC)implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.43 to +0.48 LSB and -1.62 to + 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit (FOM) of 0.63 pJ per conversion-step. 展开更多
关键词 analog-to-digital convert PIPELINE op-amp sharing CMOS bootstrapping switch hybrid compensation LOW-VOLTAGE
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An ultra high-speed 8-bit timing interleave folding&interpolating analog-to-digital converter with digital foreground calibration technology
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作者 张正平 王永禄 +5 位作者 黄兴发 沈晓峰 朱璨 张磊 余金山 张瑞涛 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第9期133-139,共7页
A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology t... A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected. 展开更多
关键词 ultra high-speed interpolation algorithm FOLDING analog-to-digital converter
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The total ionizing dose effect in 12-bit, 125 MSPS analog-to-digital converters
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作者 吴雪 陆妩 +5 位作者 李豫东 郭旗 王信 张兴尧 于新 马武英 《Journal of Semiconductors》 EI CAS CSCD 2014年第4期87-91,共5页
This paper presents the total ionizing dose test results at different biases and dose rates for AD9233, which is fabricated using a modern CMOS process. The experimental results show that the digital parts are more se... This paper presents the total ionizing dose test results at different biases and dose rates for AD9233, which is fabricated using a modern CMOS process. The experimental results show that the digital parts are more sensitive than the other parts. Power down is the worst-case bias, and this phenomenon is first found in the total ionizing dose effect of analog-to-digital converters. We also find that the AC as well as DC parameters are sensitive to the total ionizing dose at a high dose rate, whereas none of the parameters are sensitive at a low dose rate. The test facilities, results and analysis are presented in detail. 展开更多
关键词 ionizing radiation analog-to-digital converter different biases dose-rate effects
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Stability optimization of channel-interleaved photonic analog-to-digital converter by extracting of dual-output photonic demultiplexing 被引量:5
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作者 Kangjia Zheng Weiwen Zou +2 位作者 Lei Yu Na Qian Jianping Chen 《Chinese Optics Letters》 SCIE EI CAS CSCD 2020年第1期95-99,共5页
We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach... We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach–Zehnder modulator(MZM)-based photonic switch on this system was analyzed theoretically and experimentally.The feasibility of extracting feedback signals from the PADC system was derived.A high-stability channel-interleaved PADC was constructed by extracting a feedback signal from a parallel demultiplexing module to control the MZM-based photonic switch’s driving voltage.Consequently,the amplitude mismatch between the channels was limited to within 0.3 d B over 12 hours of operation. 展开更多
关键词 PHOTONIC analog-to-digital converter Mach–Zehnder modulator STABILITY OPTIMIZATION
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Dual-output modulation in time-wavelength interleaved photonic analog-to-digital converter based on actively mode-locked laser 被引量:3
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作者 张华杰 邹卫文 +1 位作者 杨光 陈建平 《Chinese Optics Letters》 SCIE EI CAS CSCD 2016年第3期18-22,共5页
This Letter demonstrates the application of dual-output modulation in a photonic analog-to-digital converter (PADC) with a high sampling rate and resolution. The PADC is time-wavelength interleaved and based on an a... This Letter demonstrates the application of dual-output modulation in a photonic analog-to-digital converter (PADC) with a high sampling rate and resolution. The PADC is time-wavelength interleaved and based on an actively mode-locked laser. According to theoretical analysis, the dual-output PADC system shows a better linearity for achieving a higher dynamic range. In the experiment, third-order distortion is significantly sup- pressed by -40 dB when the dual-output modulator is used and the effective number of bits of the PADC has reached 9.0 bits below 0.2 GHz and 6.4 bits at 6.1 GHz in our PADC with a sampling rate of 20 GS/s. 展开更多
关键词 Frequency converters Lasers Locks (fasteners) Mode locked fiber lasers MODULATION
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Ultra-wideband signal acquisition by use of channelinterleaved photonic analog-to-digital converter under the assistance of dilated fully convolutional network 被引量:5
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作者 Rui Wang Shaofu Xu +1 位作者 Jianping Chen Weiwen Zou 《Chinese Optics Letters》 SCIE EI CAS CSCD 2020年第12期88-93,共6页
We demonstrate a photonic architecture to enable the separation of ultra-wideband signals.The architecture consists of a channel-interleaved photonic analog-to-digital converter(PADC)and a dilated fully convolutional ... We demonstrate a photonic architecture to enable the separation of ultra-wideband signals.The architecture consists of a channel-interleaved photonic analog-to-digital converter(PADC)and a dilated fully convolutional network(DFCN).The aim of the PADC is to perform ultra-wideband signal acquisition,which introduces the mixing of signals between different frequency bands.To alleviate the interference among wideband signals,the DFCN is applied to reconstruct the waveform of the target signal from the ultra-wideband mixed signals in the time domain.The channel-interleaved PADC provides a wide spectrum reception capability.Relying on the DFCN reconstruction algorithm,the ultra-wideband signals,which are originally mixed up,are effectively separated.Additionally,experimental results show that the DFCN reconstruction algorithm improves the average bit error rate by nearly three orders of magnitude compared with that without the algorithm. 展开更多
关键词 ultra-wideband signal acquisition photonic analog-to-digitai converter deep learning
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Total ionizing dose effects on a radiation-induced BiMOS analog-to-digital converter 被引量:1
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作者 吴雪 陆妩 +6 位作者 王义元 胥佳灵 张乐情 卢健 于新 张兴尧 胡天乐 《Journal of Semiconductors》 EI CAS CSCD 2013年第1期94-99,共6页
The total dose effect of an AD678 with a BiMOS process is studied.We investigate the performance degradation of the device in different bias states and at several dose rates.The results show that an AD678 can endure 3... The total dose effect of an AD678 with a BiMOS process is studied.We investigate the performance degradation of the device in different bias states and at several dose rates.The results show that an AD678 can endure 3 krad(Si) at low dose rate and 5 krad(Si) at a high dose rate for static bias.The sensitive parameters to the bias states also differ distinctly.We find that the degradation is more serious on static bias.The underlying mechanisms are discussed in detail. 展开更多
关键词 BIMOS A/D converter 60Co radiation bias state dose rate
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Spurious-free dynamic range improvement in a photonic time-stretched analog-to-digital converter based on third-order predistortion 被引量:1
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作者 Boyu Xu Wulue Lv +5 位作者 Jiamu Ye Jinhai Zhou Xiaofeng Jin Xianmin Zhang Hao Chi Shilie Zheng 《Photonics Research》 SCIE EI CAS 2014年第5期97-101,共5页
Spurious-free dynamic range(SFDR)limited by intermodulation distortions is a usually accepted measure for dynamic performance of a photonic time-stretched analog-to-digital converter(ADC).In this paper,SFDR improvemen... Spurious-free dynamic range(SFDR)limited by intermodulation distortions is a usually accepted measure for dynamic performance of a photonic time-stretched analog-to-digital converter(ADC).In this paper,SFDR improvement in a photonic time-stretched ADC based on third-order predistortion is proposed.The third-order predistortion is achieved optically within an integrated dual-parallel Mach–Zehnder modulator(DPMZM).The mechanism of SFDR improvement with third-order predistortion in the DPMZM is theoretically analyzed.Compared with a conventional scheme without predistortion,the experimental results show that the SFDR improvement of∼26 dB in the proposed scheme is proved. 展开更多
关键词 convertER MODULATOR SFDR
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