With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. A...This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.展开更多
The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are inv...The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.展开更多
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital c...A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.展开更多
A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC ...A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.展开更多
针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
逐次逼近寄存器模数转换器(SAR ADC)在逐次逼近的过程中,电容的切换会使参考电压上出现参考纹波噪声,该噪声会影响比较器的判定,进而输出错误的比较结果。针对该问题,基于CMOS 0.5μm工艺,设计了一种具有纹波消除技术的10 bit SAR ADC...逐次逼近寄存器模数转换器(SAR ADC)在逐次逼近的过程中,电容的切换会使参考电压上出现参考纹波噪声,该噪声会影响比较器的判定,进而输出错误的比较结果。针对该问题,基于CMOS 0.5μm工艺,设计了一种具有纹波消除技术的10 bit SAR ADC。通过增加纹波至比较器输入端的额外路径,将参考纹波满摆幅输入至比较器中;同时设计了消除数模转换器(DAC)模块,对参考纹波进行采样和输入,通过反转纹波噪声的极性,消除参考纹波对ADC输出的影响。该设计将信噪比(SNR)提高到56.75 dB,将有效位数(ENOB)提升到9.14 bit,将积分非线性(INL)从-1~5 LSB降低到-0.2~0.3 LSB,将微分非线性(DNL)从-3~4 LSB降低到-0.5~0.5 LSB。展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器...针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。展开更多
As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although convent...As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.展开更多
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.
基金supported by the National Natural Science Foundation of China (Grant No. 11205038)the China Postdoctoral Science Foundation (Grant No. 2012M510951)
文摘The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
文摘A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.
文摘A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
文摘针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。
基金This work was supported by the National Research Foundation of Korea(NRF)grant funded by theKorea government(MSIT)(No.2022R1A5A8026986)and supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2020-0-01304,Development of Self-learnable Mobile Recursive Neural Network Processor Technology)+3 种基金It was also supported by the MSIT(Ministry of Science and ICT),Korea,under the Grand Information Technology Research Center support program(IITP-2022-2020-0-01462)supervised by the“IITP(Institute for Information&communications Technology Planning&Evaluation)”supported by the National Research Foundation of Korea(NRF)grant funded by the Korea government(MSIT)(No.2021R1F1A1061314)In addition,this work was conducted during the research year of Chungbuk National University in 2020.
文摘As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.