A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

高精度低功耗噪声整形SAR ADC设计

针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

低精度ADC下无小区大规模MIMO系统的频谱效率研究

无小区大规模多输入多输出(cell-free massive multiple-input multiple-output,CF-mMIMO)系统的覆盖区域内随机部署了大量分布式接入点(access points,APs)在同一时间频率资源中服务所有的用户,可显著提升系统通信容量,是6G网络中最具潜力的使能技术之一。然而,大量AP处配备高精度模数转换器(analog-to-digital converters,ADCs)导致的高功耗与硬件成本,限制了CF-mMIMO系统的实际部署。为了有效地降低硬件成本,本文研究了低精度ADCs下CF-mMIMO系统的上行链路频谱效率(spectral efficiency,SE)。在不完美的信道估计下,利用加性量化噪声(additive quantization noise model,AQNM)模型和最大比合并(maximal ratio combining,MRC)接收机滤波器,推导了CF-mMIMO系统中用户上行可达速率的闭式表达式,并基于该表达式分析了AP数量、用户传输功率以及ADCs精度等系统参数对SE的影响。为了最大化CF-mMIMO系统的SE,提出了一种低精度ADCs下贪婪导频分配算法抑制导频污染。将导频分配建模为最大-最小导频优化问题,通过迭代更新速率最小用户的导频序列,使其所受导频污染的影响最小,从而最大化该用户的可达速率。最后,将配备低精度ADC的CFmMIMO系统与传统完美精度ADC系统进行性能比较。数值仿真结果表明,系统配备5位低精度ADCs时的SE逼近完美精度ADCs,增加AP端天线数可以弥补低精度ADCs导致的性能退化。此外,所提算法不仅有效抑制了导频污染,还缩小了用户之间的速率差距,提升了系统的95%用户SE。

一种具有纹波消除技术的10 bit SAR ADC

逐次逼近寄存器模数转换器(SAR ADC)在逐次逼近的过程中,电容的切换会使参考电压上出现参考纹波噪声,该噪声会影响比较器的判定,进而输出错误的比较结果。针对该问题,基于CMOS 0.5μm工艺,设计了一种具有纹波消除技术的10 bit SAR ADC。通过增加纹波至比较器输入端的额外路径,将参考纹波满摆幅输入至比较器中;同时设计了消除数模转换器(DAC)模块,对参考纹波进行采样和输入,通过反转纹波噪声的极性,消除参考纹波对ADC输出的影响。该设计将信噪比(SNR)提高到56.75 dB,将有效位数(ENOB)提升到9.14 bit,将积分非线性(INL)从-1~5 LSB降低到-0.2~0.3 LSB,将微分非线性(DNL)从-3~4 LSB降低到-0.5~0.5 LSB。

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

A 1.8V 10bit 100Msps Pipelined Analog to Digital Converter

A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter （ADC） achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit （S/H） and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB （input frequency of 6.26MHz） and an SNR of 49. 8dB （input frequency of 48. 96MHz） when the sampling frequency is 100MHz.

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.

高精度高摆幅多工位ADC测试系统设计

基于V93000 ATE设计了一种采用外加电源升压变换模块及可变增益仪器仪表运算放大器,以解决大输入摆幅高精度多工位ADC的量产测试需求的测试方案。理论分析和测试验证结果表明,该ADC测试系统可分别产生峰峰值超过29 V的Ramp波和正弦波测试信号,测试信号SNR优于105 dB、THD优于-103 dB,可以满足16 bit、±10 V甚至以上高输入摆幅多工位ADC的大批量量产测试需求。

大带宽采样下通用接收机ADC设计

为了解决宽带采样通用接收机中模数转换器(ADC)的抗干扰问题,定量分析采样带宽内存在不同功率的其他信号时对有用信号量化时造成的ADC输出信噪比的损失,对ADC输出信噪比的损失与输入有用信号信噪比、中频预选滤波器带宽内信号的信干噪比、输入信号功率、有用信号带宽、ADC采样带宽、ADC量化位数的关系进行理论分析与推导,并进行多场景下的仿真验证。结果表明,研究中对ADC输入和量化噪声的理论分析及推导是正确的,对于卫星通信中带宽20 kHz的典型信号,当要求输出信噪比损失小于0.1 dB时,要实现20,30和40 dB的抗干扰能力所需要的最小量化位数分别为8位,9位和10位。宽带采样下接收机ADC的设计,可获得最佳的性价比,并利于在工程中控制成本,对于宽窄带兼容接收有一定的工程意义。

工艺-电压-温度综合稳健的亚1 V 10位SAR ADC

采用0.11-μm CMOS工艺设计了一款10位亚1 V工艺-电压-温度(Process-Voltage-Temperature,PVT)综合稳健的逐次逼近寄存器型(Successive-Approximation-Register,SAR)模数转换器(Analog-to-Digital Converter,ADC)IP核.由于SAR ADC数字化程度较高,为了降低整体功耗,采用小于标准电压的亚1 V供电.然而,对于异步SAR ADC,在低压下面临严峻的PVT不稳健问题,传统采用固定延迟电路的方式无法应对所有的PVT偏差,会导致ADC良率下降.提出一种用于异步SAR ADC的可配置延迟调控技术,采用3输入译码器调节延迟电路的电流,以满足ADC在多种PVT组合下所需的延时,在TT,SS,FF,SF,FS这5种工艺角,0.9~1 V供电范围和-40~85℃的温度范围下,均取得了良好的动态特性.在0.95 V供电,采样速率为200 kS/s时,总功耗为2.24μW,FoM值仅为16.46 fJ/Conv.-step.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.