Nullors, and Nullor Circuits;There Applications in Symbolic Circuit Analysis and Design

The objective in this presentation is to introduce some of the unique properties and applications of nullors in active circuit analysis and designs. The emphasis is to discuss the role nullors can play in symbolic representation of transfer functions. To show this we adopt the topological platform for the circuit analysis and use a recently developed Admittance Method (AM) to achieve the Sum of Tree Products (STP), replacing the determinant and cofactors of the Nodal Admittance Matrix (NAM) of the circuit. To construct a transfer function, we start with a given active circuit and convert all its controlled sources and I/O-ports to nullors. Now, with a solid nullor circuit (passive elements and nullors) we first eliminate the passive elements through AM operations. This produces the STPs. Second, the all-nullor circuit is then used to find the signs or the STPs. Finally, the transfer function (in symbolic, if chosen) is obtained from the ratio between the STPs.

Wavelet neural network based fault diagnosis in nonlinear analog circuits

The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studled. Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the signature dada. The best wavelet function is selected based on the between-category total scatter of signature. The fault dictionary of nonlinear circuits is constructed based on improved back-propagation（BP） neural network. Experimental results demonstrate that the method proposed has high diagnostic sensitivity and fast fault identification and deducibility.

Feature evaluation and extraction based on neural network in analog circuit fault diagnosis

Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The feature evaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis efficiency. A fault diagnosis illustration validated this method.

Analog circuit intelligent fault diagnosis based on GKPCA and multi-class SVM approach

Analog circuits fault diagnosis is essential for guaranteeing the reliability and maintainability of electronic systems. In this paper, a novel analog circuit fault diagnosis approach is proposed based on greedy kernel principal component analysis (KPCA) and one-against-all support vector machine (OAASVM). In order to obtain a successful SVM-based fault classifier, eliminating noise and extracting fault features are very important. Due to the better performance of nonlinear fault features extraction and noise elimination as compared with PCA, KPCA is adopted in the proposed approach. However, when we adopt KPCA to extract fault features of analog circuit, a drawback of KPCA is that the storage required for the kernel matrix grows quadratically, and the computational cost for eigenvector of the kernel matrix grows linearly with the number of training samples. Therefore, GKPCA, which can approximate KPCA with small representation error, is introduced to enhance computational efficiency. Based on the statistical learning theory and the empirical risk minimization principle, SVM has advantages of better classification accuracy and generalization performance. The extracted fault features are then used as the inputs of OAASVM to solve fault diagnosis problem. The effectiveness of the proposed approach is verified by the experimental results.

Data-driven fault diagnosis method for analog circuits based on robust competitive agglomeration

The data-driven fault diagnosis methods can improve the reliability of analog circuits by using the data generated from it. The data have some characteristics, such as randomness and incompleteness, which lead to the diagnostic results being sensitive to the specific values and random noise. This paper presents a data-driven fault diagnosis method for analog circuits based on the robust competitive agglomeration （RCA）, which can alleviate the incompleteness of the data by clustering with the competing process. And the robustness of the diagnostic results is enhanced by using the approach of robust statistics in RCA. A series of experiments are provided to demonstrate that RCA can classify the incomplete data with a high accuracy. The experimental results show that RCA is robust for the data needed to be classified as well as the parameters needed to be adjusted. The effectiveness of RCA in practical use is demonstrated by two analog circuits.

Combinatorial Optimization Based Analog Circuit Fault Diagnosis with Back Propagation Neural Network

Electronic components' reliability has become the key of the complex system mission execution. Analog circuit is an important part of electronic components. Its fault diagnosis is far more challenging than that of digital circuit. Simulations and applications have shown that the methods based on BP neural network are effective in analog circuit fault diagnosis. Aiming at the tolerance of analog circuit,a combinatorial optimization diagnosis scheme was proposed with back propagation( BP) neural network( BPNN).The main contributions of this scheme included two parts:( 1) the random tolerance samples were added into the nominal training samples to establish new training samples,which were used to train the BP neural network based diagnosis model;( 2) the initial weights of the BP neural network were optimized by genetic algorithm( GA) to avoid local minima,and the BP neural network was tuned with Levenberg-Marquardt algorithm( LMA) in the local solution space to look for the optimum solution or approximate optimal solutions. The experimental results show preliminarily that the scheme substantially improves the whole learning process approximation and generalization ability,and effectively promotes analog circuit fault diagnosis performance based on BPNN.

Characteristic test of analog integrated circuit frequency

This paper presents an analog circuit built-in-test （BIT） structure based on boundary scan and realizes the BI＇I. It predigests the test process and improves the test precision by taking the rectangular pulse as stimulator and analog switch as auxiliary bridge. The experiment of uA741 shows that the design is feasible. Compared with the traditional test method, it is better regarding reliability and measurability of the analog circuit system.

Improved RBF network application in analog circuit fault isolation

One kind of steepest descent incremental projection learning algorithm for improving the training of radial basis function(RBF)neural network is proposed,which is applied to analog circuit fault isolation.This algorithm simplified the structure of network through optimum output layer coefficient with incremental projection learning(IPL)algorithm,and adjusted the parameters of the neural activation function to control the network scale and improve the network approximation ability.Compared to the traditional algorithm,the improved algorithm has quicker convergence rate and higher isolation precision.Simulation results show that this improved RBF network has much better performance,which can be used in analog circuit fault isolation field.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

Optimized Implementation for Wave Digital Filter Based Circuit Emulation on FPGA

A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.

Design of ispPAC-based Humidity Sensor Signal Processing Circuits

The widely used sensitive elements of humidity sensors can be divided into 3 types,i.e.,resistor,capacitor,and electrolyte.Humidity sensors consisting of these sensitive elements have corresponding signal processing circuit unique to each type of sensitive elements.This paper presents an ispPAC (in-system programmable Programmable Analog Circuit) -based humidity sensor signal processing circuit designed with software method and implemented with in-system programmable simulators.Practical operation shows that humidity sensor signal processing circuits of this kind,exhibit stable and reliable performance.

Hierarchical Symbolic Analysis of Large Analog Circuits with Totally Coded Method

Symbolic analysis has many applications in the design of analog circuits. Existing approaches rely on two forms of symbolic-expression representation: expanded sum-of-product form and arbitrarily nested form. Expanded form suffers the problem that the number of product terms grows exponentially with the size of a circuit. Nested form is neither canonical nor amenable to symbolic manipulation. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. This algorithm, called totally coded method (TCM), consists of representing the symbolic determinant of a circuit matrix by code series and performing symbolic analysis by code manipulation. We describe an efficient code-ordering heuristic and prove that it is optimum for ladder-structured circuits. For practical analog circuits, TCM not only covers all advantages of the algorithm via determinant decision diagrams (DDD) but is more simple and efficient than DDD method.

Magnetic Field Feedback Circuit for Geomagnetic Field Compensation Control

In the current state of geomagnetic instrument testing,some aspects of geomagnetic instrument performance are difficult to test in the laboratory.If laboratory test results are inadequate,the instrument will have multiple problems while operating in the field,where a geomagnetic instrumentation test platform with a stable natural magnetic field is critical.Here,the magnetic field feedback circuit for geomagnetic field compensation control is studied in detail.That is,the magnetic field measured by the feedback magnetic sensor and the required working magnetic field are compared as input to the system,and the electric signal is transmitted to the feedback coil through an analog circuit to form a closed loop control,which provides compensation to control the magnetic field.Compared with the existing magnetic shielding method,the analog control circuit can achieve the realization of any working magnetic field,and it is not limited to a null magnetic field.The experimental result shows that the system compensates the earth’s magnetic field of 10,000 nT with an average error of 10.6 nT and average compensation error of 0.106%,providing a high compensation accuracy.The system also shows high sensitivity and excellent stability.The feedback circuit has achieved effective compensation control for the earth’s magnetic field.

A DVCC-Based Mixed-Mode Biquadratic Circuit

This paper introduces a mixed-mode biquadratic circuit employing DVCCs （differential voltage current conveyors） and grounded passive components. The biquadratic circuit can perform mixed-mode operation selecting the input and output terminals. And the circuit enables LP （low-pass）, BP （band-pass）, HP （high-pass）, BS （band-stop） and AP （all-pass） transfer functions by suitably choosing the input terminals. The circuit parameters o30 and Q can be tuned orthogonally through adjusting the passive components. The biquadratic circuit enjoys very low sensitivities with respect to the circuit components. The achievement example is given together with simulation results by PSPICE.

Soft Fault Diagnosis of Analog Circuit Based on Particle Swarm Optimization

A single soft fault diagnosis method for analog circuit with tolerance based on particle swarm optimization （PSO） is proposed. The parameter deviation of circuit elements is defined as the element of particle. Node-voltage incremental equations based on the sensitivity analysis are built as constraints of a linear programming （LP） equation. Through inducing the penalty coefficient, the LP equation is set as the fitness function for the PSO program. After evaluating the best position of particles, the position of the optimal particle states whether the actual parameter is within tolerance range or not. Simulation result shows the effectiveness of the method.

A Method on Analog Circuit Fault Diagnosis with Tolerance

In this paper, it is proved that the direction of the node-voltage difference vector, which is the difference between the node-voltage vector at faulty state and the one at the nominal state, is determined only by the location of the faulty clement in linear analog circuits. Considering that the direction of the node-voltage sensitivity vector is the same as the one of the node-voltage difference vector and also considering that the module of the node-voltage sensitivity vector presents the weight of the parameter of faulty element deviation relative to the voltage difference, fault dictionary is set up based on node-voltage sensitivity vectors. A decision algorithm is proposed concerned with both the location and the parameter difference of the faulty element. Single fault and multi-fault can be diagnosed while the circuit parameters deviate within the tolerance range of 10 %.

Design of Low-Voltage, Low-Power FGMOS Based Voltage Buffer, Analog Inverter and Winner-Take-All Analog Signal Processing Circuits

This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.

Chip Design of Li-Ion Battery Charger Operating in Constant-Current/Constant-Voltage Modes

A design for a Li-ion battery charger IC that can operate in a constant current-constant voltage （CC- CV） charge mode is proposed. In the CC-CV charge mode,the charger IC provides a constant charging current at the beginning, and then the charging current begins to decrease before the battery voltage reaches its final value. After the battery voltage reaches its final value and remains constant,the charging current is further reduced. This approach prevents charging the battery with full current near its saturated voltage,which can cause heating. The novel design of the core of the charger IC realizes the proposed CC-CV charge mode. The chip was implemented in a CSMC 0.6μm CMOS mixed signal process. The experimental results verify the realization of the proposed CC- CV charge mode. The voltage of the battery after charging is 4. 1833V.

Rail-to-rail op-amp with constant transconductance,SR and gain

A novel general-purpose low-voltage rail-to-rail CMOS （ complementary metal-oxide-semiconductor transistor ） operational amplifier （op-amp）is introduced, which obtains constant transconductance, slew rate and constant high gain over the entire input common mode voltage range. The proposed scheme has the potential for applications in deep submicrometer technology, as the operation of the circuit does not exclusively rely on the square-law or the linear-law of transistors. The scheme is compact and suitable for applications as VLSI cell. The rail-to- rail op-amp has been implemented in DPDM 0. 6 μm mixedsignal process. The simulations show that in the entire range of input common mode voltage, the variations in transconductance, SR and gain are 1%, 2. 3%, 1.36 dB, respectively. Based on this, the layout and tape-out are carded out. The area of layout is 0. 072 mm^2. The test results are basically consistent with the circuit simulation.

Optimal Stack Generation for CMOS Analog Modules with Parasitic and Mismatch Constraints

The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.Based on the proposed models,an optimal stack generation technique is developed to control the parasitics and mismatches,optimize the stack shape and ensure the generation of an Eulerian graph for a given CMOS analog module.An OPA circuit example is given to demonstrate that the circuit performances such as unit gain bandwidth and phase margin are enhanced by the proposed layout optimization method.