A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control ...A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control on HD3) . In this paper, a detailed design and analysis is presented for a transconductor made using this biasing technique. The transconductor, in addition, is made to offer high Gm, low power dissipation and is designed for linearly tunable Gm with current mode load as one of the applications. The circuit exhibits HD3) of less than –43.7 dB, high current efficiency of 1.18 V-1 and Gm of 390 μS at 1 VGp-p @ 50 MHz. UMC 0.18 μm CMOS process technology is used for simulation at supply voltage of 1.8 V.展开更多
The Generalized Falk Method(GFM)for coordinate transformation,together with two model-reduction strategies based on this method,are presented for efficient coupled field-circuit simulations.Each model-reduction strate...The Generalized Falk Method(GFM)for coordinate transformation,together with two model-reduction strategies based on this method,are presented for efficient coupled field-circuit simulations.Each model-reduction strategy is based on a decision to retain specific linearly-independent vectors,called trial vectors,to construct a vector basis for coordinate transformation.The reduced-order models are guaranteed to be stable and passive since the GFM is a congruence transformation of originally symmetric positive definite systems.We also show that,unlike the Pade-via-Lanczos(PVL)method,the GFM does not generate unstable positive poles while reducing the order´of circuit problems.Further,the proposed GFM is also faster when compared to methods of the type Lanczos(or Krylov)that are already widely used in circuit simulations for electrothermal and electromagnetic problems.The concept of response participation factors is introduced for the selection of the trial vectors in the proposed model-reduction methods.Further,we present methods to develop simple equivalent circuit networks for the field component of the overall field-circuit system.The implementation of these equivalent circuit networks in circuit simulators is discussed.With the proposed model-reduction strategies,significant improvement on the efficiency of the generalized Falk method is illustrated for coupled field-circuit problems.展开更多
The paper describes the application of an ANN based approach to the identification of the parameters relevant to the steady state behavior of composite power electronic device models of circuit simulation software. ...The paper describes the application of an ANN based approach to the identification of the parameters relevant to the steady state behavior of composite power electronic device models of circuit simulation software. The identification of model parameters of IGBT in PSPICE using BP neural network is illustrated.展开更多
Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The ...Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.展开更多
不间断电源(Uninterruptible Power Supply,UPS)作为电力保障系统的重要组成部分,在现代电力系统中扮演着至关重要的角色。然而,由于UPS具有复杂的电子电路结构,在实际运行中常常面临各种故障问题,不仅影响系统的可靠性和稳定性,而且可...不间断电源(Uninterruptible Power Supply,UPS)作为电力保障系统的重要组成部分,在现代电力系统中扮演着至关重要的角色。然而,由于UPS具有复杂的电子电路结构,在实际运行中常常面临各种故障问题,不仅影响系统的可靠性和稳定性,而且可能导致重大的经济损失和安全风险。因此,深入分析UPS故障,并提出有效的解决方案具有重要意义。文章通过研究基于电子电路原理的UPS故障分析与解决方案,梳理相关理论和实践经验,为UPS故障诊断与维修提供参考与指导。展开更多
文摘A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control on HD3) . In this paper, a detailed design and analysis is presented for a transconductor made using this biasing technique. The transconductor, in addition, is made to offer high Gm, low power dissipation and is designed for linearly tunable Gm with current mode load as one of the applications. The circuit exhibits HD3) of less than –43.7 dB, high current efficiency of 1.18 V-1 and Gm of 390 μS at 1 VGp-p @ 50 MHz. UMC 0.18 μm CMOS process technology is used for simulation at supply voltage of 1.8 V.
文摘The Generalized Falk Method(GFM)for coordinate transformation,together with two model-reduction strategies based on this method,are presented for efficient coupled field-circuit simulations.Each model-reduction strategy is based on a decision to retain specific linearly-independent vectors,called trial vectors,to construct a vector basis for coordinate transformation.The reduced-order models are guaranteed to be stable and passive since the GFM is a congruence transformation of originally symmetric positive definite systems.We also show that,unlike the Pade-via-Lanczos(PVL)method,the GFM does not generate unstable positive poles while reducing the order´of circuit problems.Further,the proposed GFM is also faster when compared to methods of the type Lanczos(or Krylov)that are already widely used in circuit simulations for electrothermal and electromagnetic problems.The concept of response participation factors is introduced for the selection of the trial vectors in the proposed model-reduction methods.Further,we present methods to develop simple equivalent circuit networks for the field component of the overall field-circuit system.The implementation of these equivalent circuit networks in circuit simulators is discussed.With the proposed model-reduction strategies,significant improvement on the efficiency of the generalized Falk method is illustrated for coupled field-circuit problems.
文摘The paper describes the application of an ANN based approach to the identification of the parameters relevant to the steady state behavior of composite power electronic device models of circuit simulation software. The identification of model parameters of IGBT in PSPICE using BP neural network is illustrated.
文摘Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.
文摘不间断电源(Uninterruptible Power Supply,UPS)作为电力保障系统的重要组成部分,在现代电力系统中扮演着至关重要的角色。然而,由于UPS具有复杂的电子电路结构,在实际运行中常常面临各种故障问题,不仅影响系统的可靠性和稳定性,而且可能导致重大的经济损失和安全风险。因此,深入分析UPS故障,并提出有效的解决方案具有重要意义。文章通过研究基于电子电路原理的UPS故障分析与解决方案,梳理相关理论和实践经验,为UPS故障诊断与维修提供参考与指导。
