In order to quantitatively compare the design cost and performance of various gate styles,NMOS transistors with two-edged,annular and ring gate layouts were designed and fabricated by a commercial 0.35μm CMOS process...In order to quantitatively compare the design cost and performance of various gate styles,NMOS transistors with two-edged,annular and ring gate layouts were designed and fabricated by a commercial 0.35μm CMOS process.By comparing the minimum W/L ratios and transistor areas,it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed. Furthermore,by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio,it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%.It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors,since it is targeted only toward the two-edged transistor.A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.展开更多
Hot carrier effect（HCE） is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry ...Hot carrier effect（HCE） is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation,a HCE degradation model for annular NMOS and two-edged NMOS is proposed.According to this model,we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate,and annular NMOS has more serious HCE degradation than two-edged NMOS.The design,fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.展开更多
文摘In order to quantitatively compare the design cost and performance of various gate styles,NMOS transistors with two-edged,annular and ring gate layouts were designed and fabricated by a commercial 0.35μm CMOS process.By comparing the minimum W/L ratios and transistor areas,it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed. Furthermore,by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio,it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%.It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors,since it is targeted only toward the two-edged transistor.A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.
基金Project supported by the Key Program of the National Natural Science Foundation of China(No.60836004)the Ministry of Education Creative Team Research Project,China.
文摘Hot carrier effect（HCE） is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation,a HCE degradation model for annular NMOS and two-edged NMOS is proposed.According to this model,we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate,and annular NMOS has more serious HCE degradation than two-edged NMOS.The design,fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.
