A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Application of FPGA in Process Tomography Systems

This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.

Design of 3D Active Multichannel Silicon Neural Microelectrode

To find a design method for 3D active multichannel silicon microelectrode, a microstructure of active neural recording system is presented, where two 2D probes, two integrated circuits and two spacers are microassembled on a 5 mm×7 mm silicon platform, and 32 sites neural signals can be operated simultaneously. A theoretical model for measuring the neural signal by the silicon microelectrode is proposed based on the structure and fabrication process of a single-shank probe. The method of determining the dimensional parameters of the probe shank is discussed in the following three aspects, i.e. the structures of pallium and endocranium, coupled interconnecters noise, and strength characteristic of neural probe. The design criterion is to minimize the size of the neural probe as well as that the probe has enough stiffness to pierce the endocranium. The on-chip unity-gain bandpass amplifier has an overall gain of 42 dB over a bandwidth from 60 Hz to 10 kHz; and the DC-baseline stability circuit is of high input resistance above 30 MΩ to guarantee a cutoff frequency below 100 Hz. The circuit works in stimulating or recording modes. The conversion of the modes depends on the stimulating control signal.

ASIC Design of Floating-Point FFT Processor

An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

Novel Frequency Hopping Sequences Generator Based on AES Algorithm

A novel frequency hopping(FH) sequences generator based on advanced encryption standard(AES) iterated block cipher is proposed for FH communication systems.The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security.A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying ...

Reconfigurable Communication Processor: A New Approach for Network Processor

As the traditional RISC+ASIC/ASSP approach for network processor design can not meet the today’s requirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost the performance to ASIC level while reserve the programmability of the traditional RISC based system. This paper covers both the hardware architecture and the software development environment architecture.

A lightweight hardware implementation of CRYSTALS-Kyber

The security of cryptographic algorithms based on integer factorization and discrete logarithm will be threatened by quantum computers in future.Since December 2016,the National Institute of Standards and Technology(NIST)has begun to solicit post-quantum cryptographic(PQC)algorithms worldwide.CRYSTALS-Kyber was selected as the standard of PQC algorithm after 3 rounds of evaluation.Meanwhile considering the large resource consumption of current implementation,this paper presents a lightweight architecture for ASICs and its implementation on FPGAs for prototyping.In this implementation,a novel compact modular multiplication unit(MMU)and compression/decompression module is proposed to save hardware resources.We put forward a specially optimized schoolbook polynomial multiplication(SPM)instead of number theoretic transform(NTT)core for polynomial multiplication,which can reduce about 74%SLICE cost.We also use signed number representation to save memory resources.In addition,we optimize the hardware implementation of the Hash module,which cuts off about 48%of FF consumption by register reuse technology.Our design can be implemented on Kintex-7(XC7K325T-2FFG900I)FPGA for prototyping,which occupations of 4777/4993 LUTs,2661/2765 FFs,1395/1452 SLICEs,2.5/2.5 BRAMs,and 0/0 DSP respective of client/server side.The maximum clock frequency can reach at 244 MHz.As far as we know,our design consumes the least resources compared with other existing designs,which is very friendly to resource-constrained devices.

Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

A low-power and low-cost advanced encryption standard （AES） coprocessor is proposed for Zigbee system-on-a-chip （SoC） design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and decryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine （FSM） and clock gating （CG） technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor （CMOS） technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz, and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.