Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements.

Development of an Integrated CMUTs-Based Resonant Biosensor for Label-Free Detection of DNA with Improved Selectivity by Ethylene-Glycol Alkanethiols

Gravimetric resonant-inspired biosensors have attracted increasing attention in industrial and point-ofcare applications,enabling label-free detection of biomarkers such as DNA and antibodies.Capacitive micromachined ultrasonic transducers(CMUTs)are promising tools for developing miniaturized highperformance biosensing complementary metal–oxide–silicon(CMOS)platforms.However,their operability is limited by inefficient functionalization,aggregation,crosstalk in the buffer,and the requirement for an external high-voltage(HV)power supply.In this study,we aimed to propose a CMUTs-based resonant biosensor integrated with a CMOS front–end interface coupled with ethylene–glycol alkanethiols to detect single-stranded DNA oligonucleotides with large specificity.The topography of the functionalized surface was characterized by energy-dispersive X-ray microanalysis.Improved selectivity for onchip hybridization was demonstrated by comparing complementary and non-complementary singlestranded DNA oligonucleotides using fluorescence imaging technology.The sensor array was further characterized using a five-element lumped equivalent model.The 4 mm^(2) application-specific integrated circuit chip was designed and developed through 0.18 lm HV bipolar-CMOS-double diffused metal–oxide–silicon(DMOS)technology(BCD)to generate on-chip 20 V HV boosting and to track feedback frequency under a standard 1.8 V supply,with a total power consumption of 3.8 mW in a continuous mode.The measured results indicated a detection sensitivity of 7.943×10^(-3) lmol·L^(-1)·Hz^(-1) over a concentration range of 1 to 100 lmol·L^(-1).In conclusion,the label-free biosensing of DNA under dry conditions was successfully demonstrated using a microfabricated CMUT array with a 2 MHz frequency on CMOS electronics with an internal HV supplier.Moreover,ethylene–glycol alkanethiols successfully deposited self-assembled monolayers on aluminum electrodes,which has never been attempted thus far on CMUTs,to enhance the selectivity of bio-functionalization.The findings of this study indicate the possibility of full-on-chip DNA biosensing with CMUTs.

A VLIW Architecture Stream Cryptographic Processor for Information Security

As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

A Reconfigurable Block Cryptographic Processor Based on VLIW Architecture

An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.

Low Power Single-Chip RF Transceiver for Human Body Cormunication

Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency （RF） application-specific integrated circuit transceiver tbr Human Body Commnunication （HBC） is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying （OOK）/Frequency-Shift Keying （FSK） modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.

Efficient Energy Optimized Faithful Adder with Parallel Carry Generation

Abstract:Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications.This work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry(PC)generation logic.For‘n’bits in input,the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits.A simple OR logic with no carry propagation is used to implement the approximate part.In the exact part,addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical path.Evaluations reveal that the maximum error of the proposed adder confines not more than 2n/2.As an enhancement of the proposed algorithm,we use the Error Recovery(ER)module to reduce the average error.Synthesis results of Proposed-PC(P-PC)and Proposed-PCER(P-PCER)adders with n-16 in 180nm Application Specific Integrated Circuit(ASIC)PDK technology revealed 44.2%&41.7%PDP reductions and 43.4%&40.7%ADP reductions,respectively compared to the latest best approximate design compared.The functional and driving effectiveness of proposed adders are examined through digital image processing applications.

Chip Layout for Adaptive Line Enhancer Design using Adaptive Filtering Algorithms and Metrics Computation for Auscultation Signal Separation

Currently,the growth of micro and nano(very large scale integration-ultra large-scale integration)electronics technology has greatly impacted biomedical signal processing devices.These high-speed micro and nano technology devices are very reliable despite their capacity to operate at tremendous speed,and can be designed to consume less power in minimum response time,which is particularly useful in biomedical products.The rapid technological scaling of the metal-oxide-semi-conductor(MOS)devices aids in mapping multiple applications for a specific purpose on a single chip which motivates us to design a sophisticated,small and reliable application specific integrated circuit(ASIC)chip for future real time medical signal separation and processing(digital stetho-scopes and digital microelectromechanical systems(MEMS)microphone).In this paper,ASIC level implementation of the adaptive line enhancer design using adaptive filtering algorithms(least mean square(LMS)and normalized least mean square(NLMS))integrated design is used to separate the real-time auscultation sound signals effectively.Adaptive line enhancer(ALE)design is imple-mented in Verilog hardware description language(HDL)language to obtain both the network and adaptive algorithm in cadence Taiwan Semiconductor Manufacturing Company(TSMC)90 nm standard cell library environment for ASIC level implementation.Native compiled simulator(NC)sim and RC lab were used for functional verification and design constraints and the physical design is implemented in Encounter to obtain the Geometric Data Stream(GDS II).In this architecture,the area occupied is 0.08 mm,the total power consumed is 5.05 mW and the computation time of the proposed system is 0.82μs for LMS design and the area occupied is 0.14 mm,the total power consumed is 4.54 mW and the computation time of the proposed system is 0.03μs for NLMS design that will pave a better way in future electronic stethoscope design.

Modern Monitoring Intraocular Pressure Sensing Devices Based on Application Specific Integrated Circuits

Glaucoma is a neurodegenerative condition that is the leading cause of irreversible blindness worldwide. Elevated intraocular pressure (IOP) is the main risk factor for the development and progression of the disease. Methods to lower IOP remain the first line treatments for the condition. Current methods of IOP measurement do not permit temporary noninvasive monitoring 24-hour IOP on a periodic basis. Ongoing research will in time provide a means of developing a device that will enable continuous or temporary monitoring of IOP. At present a device suitable for clinical use is not yet available.This review contains a description of different devices currently in development for measuring IOP: soft contact lens, LC resonant circuits and on-chip sensing devices. All of them use application-specific integrated circuits (ASICS) to process the measured signals and send them to recording devices. Soft contact lens devices are based on an embedded strain gauge, LC circuits vary their resonance frequency depending on the intraocular pressure (IOP) and, finally, on-chip sensing devices include an integrated microelectromechanical sensor (MEMS). MEMS are capacitors whose capacity varies with IOP. These devices allow for an accurate IOP measurement (up to +/– 0.2 mm Hg) with high sampling rates (up to 1 sample/min) and storing 1 week of raw data. All of them operate in an autonomous way and even some of them are energetically independent.

A sub-milliwatt audio-processing platform for digital hearing aids

We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit applicationspecific instruction-set processor （ASIP） and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP＇s instruction set to deal with some core tasks of hearing aid algorithms. The five configurable accelerators are used to execute several of the most common functions of hearing aids. Moreover, several low power strategies, such as clock gating, data isolation, memory partition, bypass mode, sleep mode, are also applied in this platform for power reduction. The proposed platform is implemented in CMOS 130 nm technology, and test results show that power consumption of FlexEngine is 0.863 mW with the clock frequency of 8 MHz at Vdd = 1.0 V.