We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low late...We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low latency.The system,housed inside a VPX-6U chassis,includes multiple arbitrary-waveform generator(AWG)channels,analog-digital-converter(ADC)channels as well as direct current source channels.The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis,and control and readout of more and more qubit can be carried out by interconnecting the chassis.By using field programmable gate array(FPGA)processors,the system incorporates three features that are specifically useful for superconducting qubit research.Firstly,qubit signals can be processed using the on-board FPGA after being acquired by ADCs,significantly reducing data processing time and data amount for storage and transmission.Secondly,different output modes,such as direct output and sequential output modes,of AWG can be implemented with pre-encoded FPGA.Thirdly,with data acquisition ADCs and control AWGs jointly controlled by the same FPGA,the feedback latency can be reduced,and in our test a 178.4 ns latency time is realized.This is very useful for future quantum feedback experiments.Finally,we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.展开更多
基金Project supported by the State Key Development Program for Basic Research of China(Grants Nos.2017YFA0304300 and 2016YFA0300600)the Natural Science Foundation of Beijing,China(Grant No.Z190012)+1 种基金the Key-Area Research and Development Program of Guangdong Province,China(Grant No.2020B0303030001)the Strategic Priority Research Program of Chinese Academy of Sciences(Grant No.XDB28000000).
文摘We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low latency.The system,housed inside a VPX-6U chassis,includes multiple arbitrary-waveform generator(AWG)channels,analog-digital-converter(ADC)channels as well as direct current source channels.The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis,and control and readout of more and more qubit can be carried out by interconnecting the chassis.By using field programmable gate array(FPGA)processors,the system incorporates three features that are specifically useful for superconducting qubit research.Firstly,qubit signals can be processed using the on-board FPGA after being acquired by ADCs,significantly reducing data processing time and data amount for storage and transmission.Secondly,different output modes,such as direct output and sequential output modes,of AWG can be implemented with pre-encoded FPGA.Thirdly,with data acquisition ADCs and control AWGs jointly controlled by the same FPGA,the feedback latency can be reduced,and in our test a 178.4 ns latency time is realized.This is very useful for future quantum feedback experiments.Finally,we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
