The online diagnosis for aircraft system has always been a difficult problem. This is due to time evolution of system change, uncertainty of sensor measurements, and real-time requirement of diagnostic inference. To a...The online diagnosis for aircraft system has always been a difficult problem. This is due to time evolution of system change, uncertainty of sensor measurements, and real-time requirement of diagnostic inference. To address this problem, two dynamic Bayesian network(DBN) approaches are proposed. One approach prunes the DBN of system, and then uses particle filter(PF) for this pruned DBN(PDBN) to perform online diagnosis. The problem is that estimates from a PF tend to have high variance for small sample sets. Using large sample sets is computationally expensive. The other approach compiles the PDBN into a dynamic arithmetic circuit(DAC) using an offline procedure that is applied only once, and then uses this circuit to provide online diagnosis recursively. This approach leads to the most computational consumption in the offline procedure. The experimental results show that the DAC, compared with the PF for PDBN, not only provides more reliable online diagnosis, but also offers much faster inference.展开更多
An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications wi...An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZDIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits.展开更多
基金Projects(2010ZD11007,20100751010)supported by Aeronautical Science Foundation of China
文摘The online diagnosis for aircraft system has always been a difficult problem. This is due to time evolution of system change, uncertainty of sensor measurements, and real-time requirement of diagnostic inference. To address this problem, two dynamic Bayesian network(DBN) approaches are proposed. One approach prunes the DBN of system, and then uses particle filter(PF) for this pruned DBN(PDBN) to perform online diagnosis. The problem is that estimates from a PF tend to have high variance for small sample sets. Using large sample sets is computationally expensive. The other approach compiles the PDBN into a dynamic arithmetic circuit(DAC) using an offline procedure that is applied only once, and then uses this circuit to provide online diagnosis recursively. This approach leads to the most computational consumption in the offline procedure. The experimental results show that the DAC, compared with the PF for PDBN, not only provides more reliable online diagnosis, but also offers much faster inference.
基金the National Natural Science Foundation of China (No. 90207002)
文摘An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZDIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits.
