Design and implementation of instruction-driven and data-driven self-reconfigurable cell array

The reconfigurable chip,which integrates the advantages of high performance,high flexibility,high parallelism,low power consumption,and low cost,has achieved rapid development and wide application.Generally,the control part and the computing part of algorithm is accelerated based on different reconfigurable architectures,but it is difficult to obtain overall performance improvement.For improving efficiency of reconfigurable structure both for the control part and the computing part,a hybrid of instruction-driven and data-driven self-reconfigurable cell array is proposed.On instruction-driven mode,processing element(PE)works like a reduced instruction set computer(RSIC)machine,which is mainly for the control part of algorithm.On data-driven mode,data is calculated by flowing between the preconfigured PEs,which is mainly for the computing of algorithm.For verifying the efficiency of architecture,some high-efficiency video coding(HEVC)video compression algorithms are implemented on the proposed architecture.The proposed architecture has been implemented on Xilinx FPGA Virtex UltraScale VU440 develop board.The same circuitry is able to run at75 MHz.Compared with the architecture that only supports instruction-driven,the proposed architecture has better calculation efficiency.

Composite Semiconductor Quantum Dots CdSe/CdS Co-sensitized TiO_2 Nanorod Array Solar Cells

CdSe/CdS semiconductor quantum dots co-sensitized TiO2 nanorod array was fabricated on the transparent conductive fluorine-doped tin oxide （FTO） substrate using the hydrothermal and successive ionic layer adsorption and reaction （SILAR） process. The structural and morphological properties of the samples were characterized by X-ray diffraction （XRD）, field-emission scanning electron microscopy （FESEM）, and transmission electron microscopy （TEM）. The results indicate that CdSe/CdS QDs are uniformly coated on the surface of the TiO2 nanorods. The shift of light absorption edge was monitored by taking UV-visible absorption spectra. Compared with the absorption spectra of the TiO2 nanorod array, deposition of CdSe/CdS QDs shifts the absorption edge to the higher wavelength. The enhanced light absorption in the visible-light region of CdSe/CdS/TiO2 nanorod array indicates that CdSe/CdS layers can act as co-sensitizers in quantum dots sensitized solar cells （QDSSCs）. By optimizing the CdSe layer deposition cycles, a photocurrent of 5.78 mA/cm2, an open circuit photovoltage of 0.469 V and a conversion efficiency of 1.34 % were obtained under an illumination of 100 mw/cm2.

Dynamical Self-Reconfigurable Mechanism for Data-Driven Cell Array

The utilization of computation resources and reconfiguration time has a large impact on reconfiguration system performance. In order to promote the performance, a dynamical self-reconfigurable mechanism for data-driven cell array is proposed. Cells can be fired only when the needed data arrives, and cell array can be worked on two modes: fixed execution and reconfiguration. On reconfiguration mode, cell function and data flow direction are changed automatically at run time according to contexts. Simultaneously using an H-tree interconnection network, through pre-storing multiple application mapping contexts in reconfiguration buffer, multiple applications can execute concurrently and context switching time is the minimal. For verifying system performance, some algorithms are selected for mapping onto the proposed structure, and the amount of configuration contexts and execution time are recorded for statistical analysis. The results show that the proposed self-reconfigurable mechanism can reduce the number of contexts efficiently, and has a low computing time.

A New Method of Solving Kernels in Algebraic Decomposition for the Synthesis of Logic Cell Array

In this paper, an improvement has been made on the algorithm of solving the kernels of new functions which are generated after a common divisor appearing in the original functions is replaced by a new intermediate variable. And an efficient method based on kernel heritage is presented. This method has been successfully used in synthesis of LCA (Logic Cell Array).

Image reconstruction for brain CT slices

Different modalities in biomedical images, like CT, MRI and PET scanners, provide detailed cross-sectional views of human anatomy. This paper introduces three-dimensional brain reconstruction based on CT slices. It contains filtering, fuzzy segmentation, matching method of contours, cell array structure and image animation. Experimental results have shown its validity. The innovation is matching method of contours and fuzzy segmentation algorithm of CT slices.

Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array

The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes. Traditional reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices (RCDs) consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU. © 2017, Shanghai Jiaotong University and Springer-Verlag GmbH Germany.

Efficient Scheduling Mapping Algorithm for Row Parallel Coarse-Grained Reconfigurable Architecture

Row Parallel Coarse-Grained Reconfigurable Architecture(RPCGRA)has the advantages of maximum parallelism and programmable flexibility.Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints.To solve this problem,the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA.In this paper,we present a Depth-First Greedy Mapping(DFGM)algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array(RCA).Compared with level breadth mapping,the performance of DFGM is better.The percentage of maximum improvement in the use times of RCA is 33%and the percentage of maximum improvement in non-original input and output times is 64.4%(Given Discrete Cosine Transfor 8(DCT8),and the area of reconfigurable processing unit is 56).Compared with level-based depth mapping,DFGM also obtains the lowest averages of use times of RCA,non-original input and output times,and the reconfigurable time.