For the purpose of resolving the problem of performance deterioration introduced by inaccurate phase compensation in existing coherent averaging line spectrum detectors, a modified coherent detector is proposed. The t...For the purpose of resolving the problem of performance deterioration introduced by inaccurate phase compensation in existing coherent averaging line spectrum detectors, a modified coherent detector is proposed. The three point interpolation in frequency domain is applied to obtain accurate estimate of phase difference between segments when the segmented length is not an integral multiple of the signal period. Then the segmented data are multiplied by a complex coefficient to remove the phase difference and synchronize the phases of all the segments before coherent averaging. Theoretical analysis shows that there will be a gain of 3.9 dB at most by using the modified detector. The detection performance of the incoher- ent averaging power spectrum detector （AVGPR）, the phase coherent averaging detector, the modified coherent averaging detector are compared with each other by computer simulations. The results coincide basically with the theoretical analysis, which show the superiority of the modified detector to the former two detectors.展开更多
This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpo...This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network. Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution. In SMIC 0.18 μm CMOS, the A/D converter is measured as follows： the peak integral nonlinearity and differential nonlin- earity are 4-0.48 LSB and 4-0.33 LSB, respectively. Input range is 1.0 Vp-p with a 2.29 mm2 active area. At 20 MHz input @ 100 MHz sample clock, 9.59 effective number of bits, 59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved. The dissipation power is only 95 mW with a 1.8 V power supply.展开更多
文摘For the purpose of resolving the problem of performance deterioration introduced by inaccurate phase compensation in existing coherent averaging line spectrum detectors, a modified coherent detector is proposed. The three point interpolation in frequency domain is applied to obtain accurate estimate of phase difference between segments when the segmented length is not an integral multiple of the signal period. Then the segmented data are multiplied by a complex coefficient to remove the phase difference and synchronize the phases of all the segments before coherent averaging. Theoretical analysis shows that there will be a gain of 3.9 dB at most by using the modified detector. The detection performance of the incoher- ent averaging power spectrum detector （AVGPR）, the phase coherent averaging detector, the modified coherent averaging detector are compared with each other by computer simulations. The results coincide basically with the theoretical analysis, which show the superiority of the modified detector to the former two detectors.
基金supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028)the National High-Tech Research and Development Program of China(No.2009AA01Z258)the National Science & Technology Important Project of China (No.2009ZX01034-002001-005)
文摘This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network. Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution. In SMIC 0.18 μm CMOS, the A/D converter is measured as follows： the peak integral nonlinearity and differential nonlin- earity are 4-0.48 LSB and 4-0.33 LSB, respectively. Input range is 1.0 Vp-p with a 2.29 mm2 active area. At 20 MHz input @ 100 MHz sample clock, 9.59 effective number of bits, 59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved. The dissipation power is only 95 mW with a 1.8 V power supply.
